tails4e

29 ms·

361.
by tails4e 6y ago
Vivado. It's for FPGA design, and I while do ASIC design, but I use vivado to visualise my RTL structure. I find it better than any of the major EDA vendors RTL schematic viewers (except perhaps starvision). I know people rag on Vivado
362.
by tails4e 6y ago
Being fabless has quite a few advantages too, the cost of building / running a fab is huge, so can only be afforded by major player, or folks who can live on very old process nodes. Most startups, and even ADI themselves use the later
363.
by tails4e 6y ago
The power problem is solved by having cores more suited to a task. A CPU is completely general, but power inefficient. Dedicated HW is as efficient as it gets, but in the extreme is not flexible and only does one task well. With loads of ex
364.
by tails4e 6y ago
Jim Keller had an interesting talk recently [1] about ways of doing parallel processing to better us the billions of transistors we have - assuming the task is parallelizable. There's the scalar core (i.e the basic CPU) which is easy t
365.
by tails4e 6y ago
Moore's Law really has 2 aspects - scaling and economic. The original quote states: "The complexity for minimum component costs has in- creased at a rate of roughly a factor of two per year". This basically says things scale
366.
by tails4e 6y ago
They are still OK, IC aging only occurs when it's active. So a chip designed for 10 years expires after 10 years of use. If you occasionally plug in that old console, it will be fine. It's likely other things will expire first in
367.
by tails4e 6y ago
We make ICs and target 20 year lifespan. A lot of cost and over-design goes into achieving that MTBF, especially if a device only had a typical usable lifespan much shorter. ECU should be 30 years, but a GPU, probably not. Will you be gamin
368.
by tails4e 6y ago
Is there a solid solution to the SD card problem? Every Rpi I've tried to use as a server eventually kills its SD card, probably as running an os on SD is destined for failure with write wear. I'm guessing using SD for boot only a
369.
by tails4e 6y ago
It does beg the question of SEU, ie single event upsets, which cause bits of digital circuits to randomly flip, and is much worse at altitude (another nice thing out atmosphere does for us) Circuits must be designed to be rad-hard to be les
370.
by tails4e 6y ago
I've a precision 5530. On paper it's a lovely machine. In practice, lots of graphics issues, docking station issues where screens flicker, etc. It's such a shame for something so costly. It's a work laptop, I'd have
371.
by tails4e 6y ago
That's very well done, thanks for sharing. I really like the straight forward writing style, I've never attempted to write a compiler, and have only done basic parsers for day to day tasks, so like the clean, simple approach.
372.
by tails4e 6y ago
That's a good point,the dataflow can be confusing to understand at first, especially when used to a purely procedural paradigm. In a way its similar to the differences between functional and imperative programming, and you first need t
373.
by tails4e 6y ago
I Fully agree. Learning Verilog, or ideally SystemVerilog, to a basic level is important to have as a foundation for when you may need to build more advanced designs. I'm in favour of more high level languages being developed for HW ge
374.
by tails4e 6y ago
This is explicitly security oriented code. The release notes indicate a high awareness of security issues and discuss some advanced topics and items its trying to mitigate.... and then the code has a way of leaking kernel memory. Do you rea
375.
by tails4e 6y ago
Why not both? Pepper the code with easy to find (and use) vulnerabilities and also a few harder to find. It's win win for those who are trying to inject the exploits, as if the obvious stuff can be chalked down to incompetence, then th
376.
by tails4e 6y ago
Transistors are either on or off in digital circuits, ideally. A simple inverter is two transistors stacked on top, one connects the output to ground when on, the other connects the output to vdd (the supply voltage) when on. Of course only
377.
by tails4e 6y ago
This guy is seriously impressive. As the article mentions the BSIM models developed by him at Berkeley are the corner stone of all transistor simulations today, modelling thousands of subtle effects - an impressive feat, not only to build t
378.
by tails4e 7y ago
Theres a load of documentation, videos and examples, both on github maintained by xilinx as well as on xilinx.com. For example: https://www.xilinx.com/support/university.html and linked from there is a complete course
379.
by tails4e 7y ago
Xilinx are not just writing software, they also must use R&D to develop the FPGA hardware, dev kits, IP, etc, so it's a very different scale to JetBrains' focus. Also in terms of Sofware, the really challenging aspects are und
380.
by tails4e 7y ago
Hardware design flows are complex and do have bugs, but not in the way it sounds. In general HDL synthesis produces a design that matches what the user wrote, so a logic bug in a synthesis engine is rare. The bugs exist in the 'other s
381.
by tails4e 7y ago
Yes, hardware must be right first time. Proving that is difficult, so logic equivalence, formal proof, code coverage are all standard. What's optional in many software QA flows would be absolutely required in HW flows. Proof of functio
382.
by tails4e 7y ago
This may be true in some cases, but from my experience (nearly 20 years in custom IC design) good design is still more difficult than verification. Verification seems to have an element of over complication. I've seen simple, totally i
383.
by tails4e 7y ago
Verilog for writing RTL is fine, especially if you use the syhthesizable subset of SystemVerilog. There used to be a bit of a religious war between VHDL and Verilog, as VHDL had some syntax that prevented certain errors, but with SV and som
384.
by tails4e 7y ago
I'd say I'm lucky to get an hour a day that's free to actually do engineering work, 3 hours would be a godsend, and rare. Its definitely hard to be effective as an engineer with such little time to deeply engage. Ive sometime
385.
by tails4e 7y ago
Moores law has both scaling and economic aspects. Folks seem to focus on the scaling, which to a degree is still happening, but the economic aspect has not been true for the last few nodes
386.
by tails4e 7y ago
Exactly. Advertising in traditional mediums has been controlled and kept (mostly) honest for years, and this standard should be maintained and carried to all mediums. In fact some countries have much stricter regulations on advertising than
387.
by tails4e 7y ago
In this case she is a teacher in CT with very good benefits, but her husband, while on a decent salary has pretty terrible benefits, so she could not switch to his insurance is she stayed at home. Crazy situation when you think about it
388.
by tails4e 7y ago
I think you are mis- characterizing the European systems. I say systems as each country is different - some better than others for sure, but from what I've seen from both the US and European systems, I prefer the ones where my family g
389.
by tails4e 7y ago
Delighted to see strncat there, it's a buffer overflow waiting to happen, especially as the name sounds like it's the 'safer version' where it takes a size argument, except it's not the size of the destination buffe
390.
by tails4e 7y ago
The leaf is good and certainly helped, but in a way it alone (without the tesla model s/x) may have held back the mainstream adoption of electric cars as it had not dramatically addressed the challenges of battery degradation, charging

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