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I Fully agree. Learning Verilog, or ideally SystemVerilog, to a basic level is important to have as a foundation for when you may need to build more advanced de
by tails4e 6y ago
I Fully agree. Learning Verilog, or ideally SystemVerilog, to a basic level is important to have as a foundation for when you may need to build more advanced designs. I'm in favour of more high level languages being developed for HW generation, but I've yet to see a true replacement language for the main HDLs. For a counter and blinking led example, Verilog is very easy to read/understand for a beginner.
- Traster 6y agoI would always say that the important thing is the paradigm you need to adopt when writing RTL. Whether it's VHDL or systemverilog, the differences are details. It's like programming C# vs Java, they have the same core concepts. But if you hand a C# Developer VHDL/SystemVerilog/Prolog they're not going to have a good time.
- tails4e 6y agoThat's a good point,the dataflow can be confusing to understand at first, especially when used to a purely procedural paradigm. In a way its similar to the differences between functional and imperative programming, and you first need the right mindset/basis for how it works before you can be productive. Once you understand the concurrent nature being described by HDLs, it begins to make sense - I always elaborate my HDL (actually usually other folks code) so I can see the dataflow that's being inferred graphically and it's very useful