tails4e

34 ms·

331.
by tails4e 6y ago
FPGAs are way more than a few LUTs, the routing is complex, but must be efficient, there are many many hard blocks required to be useful (memories, dsp, transceivers, multi-standard IO, flexible programmable clock networks, clock generation
332.
by tails4e 6y ago
This is priceless, "electronics is trivial". You clearly saw a few logic gates and determined that was all there is to know. I would say ASIC design is more difficult than most SW, and you have to get it right first time, no patch
333.
by tails4e 6y ago
I guess my perspective comes from the other side, ASIC tools that do the same thing (synthesis, place and route, STA, simulation) are way, way worse. Design compiler was designed in the 90s, and while it has many advanced features, it&#x27
334.
by tails4e 6y ago
What do you think of the Xilinx HLS tool, I've only played with examples, but the c code being input looks like regular C, and can generate hardware (though you need pragmas to guide it for max efficiency)
335.
by tails4e 6y ago
The issue I see is they are slow to compile. I write them daily and it's not that hard to lean when you grok the parallel nature, but generating the HW usually takes at least 10 to 30 mins for a medium sized block, that is a bit of a b
336.
by tails4e 6y ago
Vivado is amazing. TCL is chosen because its portable across almost All EDA tools, so by using it, Xilinx are ensuring your existing HW design skills apply to FPGA tools also, instead of the proprietary interfaces ISE used. So while TCL is
337.
by tails4e 6y ago
Tcl is the de facto scripting standard for EDA (it's in thr name!), it's a quirky language, but what Xilinx has done is allow portability and compatability between it and major HW design tools. The low levels commands themselves a
338.
by tails4e 6y ago
Yep, emulation is huge. HAPS by Synoosys for example has a bunch of huge Xilinx FPGAs in there. I've never used one, but apparently it takes care of splitting the huge ASIC design over the array of FPGAs so it looks like a single chip,
339.
by tails4e 6y ago
I thought Xilinx would buy AMD when AMD was at $9. How the tables have sure turned.
340.
by tails4e 6y ago
If its so trivial, why isn't there a decent competitor from all the startups? Even Altera with Intels moneybags has not managed to push past. Xilinx has a data center play, new HW with arrays of processors with local memory, RF integra
341.
by tails4e 6y ago
Stacked silicon is a thing, DRAM is already stacked 32 or even 64 layers, but for logic chips even those are being stacked - HBM can be a memory die stacked on a logic die, and there are so called 3d-ICs which can stack either active on act
342.
by tails4e 6y ago
It's recently been renamed dynamic function exchange (marketing I guess?) but it'd supported in xilinx 7 series and later: https://www.xilinx.com/products/design-tools/vivado/implemen...
343.
by tails4e 6y ago
Active partial reconfiguration is a thing and works pretty much as you say - some parts of the chip continue running while others are swapped out, and an example use case is video encoding, just swap in the encoder engine optimised to a giv
344.
by tails4e 6y ago
Excellent write up and reverse engineering. Amazing to see this level of detail for an iconic chip
345.
by tails4e 6y ago
The problem is the technology too. For the first time in history can two people see the same information source (in this case Facebook) but see two completely different worlds, as each one gets their own bubble, and that bubble is biased. I
346.
by tails4e 6y ago
This is interesting, the use case I was thinking about is EDA SW, which is very expensive and performance (runtime) can be days in some cases. In the tool installs I only ever see i386 and x86_64. In curious if the EDA vendors have compiled
347.
by tails4e 6y ago
I've always wondered, if I compile an application and don't specify the architecture as explicitly having AVX, just say x86 64bit, will alternate code paths be in the binary for processors with AVX? Or alternatively, if I do speci
348.
by tails4e 6y ago
What's interesting is while this is happening I'm seeing a strong push in placed like reddit for folks to register to vote by mail. It kind of feels like election interference - intentionally slow down the mail, and at the same ti
349.
by tails4e 6y ago
Capacitative adding and subtracting is how many ADC (analog to digital converter) and DAC (digital to analog converter) chips work. There are many architectures, but capacitor arrays that are binary weighted are common, by switching them yo
350.
by tails4e 6y ago
Modern tools pale in comparison to hand laid out designs, so if something is very smart to save area, it's unlikely it was machine created.
351.
by tails4e 6y ago
That's definitely an anomaly, I use vivado with ASIC code reguarly, very large designs and have not seen anything like this. I use vivado to elaborate and a analyse code intended for ASIC use as its better than other ASIC tools for tha
352.
by tails4e 6y ago
Vivado is amazing compared with the ASIC counterparts: Design compiler is for RTL synthesis only and you need years of experience to get any decent qor out of it. In ASIC land you have separate tools for every step, synthesis, STAs, PnR, si
353.
by tails4e 6y ago
There absolutely is. There are PCIe cards you can plugin and use them as accelerators, just like you would use a GPU. Of course programming them to do the task you want is harder, but it can do anything. Saw a great example where someone im
354.
by tails4e 6y ago
I posted this elsewhere, there are a lot of good resources and examples for the tools: https://github.com/xupgit/FPGA-Design-Flow-using-Vivado/tree... https://www.xilinx.com/support/university
355.
by tails4e 6y ago
Thanks. That's very poor alright, I'll keep a note of it.
356.
by tails4e 6y ago
Thanks for the detailed reply, but FYI the github stuff is from xilinx, they just make it open source. In 2015 vivado was pretty new, it's come a long way, so I'd give it another look. There has been a strong push as you can see t
357.
by tails4e 6y ago
I rarely use the search, but when I do I've never noticed it to not find what I know is there. Perhaps it is crap and there are many other hits its not returning for my searches - can you give an example of a bad search result you got?
358.
by tails4e 6y ago
Theres loads of docs and step by step tutorials [0] is just one such free set of material with all files, with step by step PDFs and presentations to explain basic digital design concepts. This is just one form this larger list of courses [
359.
by tails4e 6y ago
I hear this a lot, but I really don't get it. The ide is very responsive, when you are interacting with a design, exploring structure or connectivity, static timing analysis, etc.. Perhaps you are referring to synthesising RTL - yes th
360.
by tails4e 6y ago
Confluence. It's so easy to organise information and documentation now for technical projects. Of course its free form so people can be messy with it, but done right, and with the good plugins, like draw.io it's really powerful. I

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