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Vivado is amazing. TCL is chosen because its portable across almost All EDA tools, so by using it, Xilinx are ensuring your existing HW design skills apply to F

Vivado is amazing. TCL is chosen because its portable across almost All EDA tools, so by using it, Xilinx are ensuring your existing HW design skills apply to FPGA tools also, instead of the proprietary interfaces ISE used. So while TCL is not a language I like, it is the HW standard so it must be in any serious EDA tool. I use many EDA tools daily (design compiler, primetime, icc2, vcs, xcelium, verdi, redhawk, and vivado) all have TCL, so some scripts are portable between tools, which is I assume why Xilinx chose to also have some command compatability with the Synopsys commands. So doing this makes HW design skills portable, which I really appreciate. This was also why they moved to XDC constraints from the UCF, embraching existing standards to help engineers.

rcxdude 6y ago
I'm not sure about amazing (there's certainly worse FPGA tools though), but I think you're right on TCL. It's still a perfectly servicable language to do the job and it's ubiquitous in the industry so you'd need a pretty strong reason to break from it. The terribleness of the tooling comes from other sources (mainly its sheer opaqueness, followed by bugginess, followed and excacerbated by its slowness, though the last point may be hard to get around: place-and-route is not like compiler optimisation, compiler optimisation is almost entirely local decisions, wheras place and route is essentially a global optimisation problem).
- tails4e 6y ago
  I guess my perspective comes from the other side, ASIC tools that do the same thing (synthesis, place and route, STA, simulation) are way, way worse. Design compiler was designed in the 90s, and while it has many advanced features, it's usability is incredibly poor. A million variables you never heard of, and each one tweaks its behaviour in weird and wonderful ways, and a GUI that still looks like its from the 90s. Costs 90k a seat to boot, but if you're doing ASIC design, it's one of the major tools you will use. And it just does the synthesis bit. Vivado does it all, and has seamless cross probing between each stage, right back to source code. It's usability to me is refreshing. I have found bugs, sure, but never a show stopper. It's free Verilog simulator (xsim) is better than any other free system Verilog simulator out there, and that's just one sub component of Vivado.
  - rcxdude 6y ago
    oh yeah, by all accounts ASIC design tools are even worse. But from a software perspective FPGA tooling is still in the dark ages from most perspectives (and the frustrating thing is a lot of it wouldn't be very hard to do better).

rcxdude 6y ago

I'm not sure about amazing (there's certainly worse FPGA tools though), but I think you're right on TCL. It's still a perfectly servicable language to do the job and it's ubiquitous in the industry so you'd need a pretty strong reason to break from it. The terribleness of the tooling comes from other sources (mainly its sheer opaqueness, followed by bugginess, followed and excacerbated by its slowness, though the last point may be hard to get around: place-and-route is not like compiler optimisation, compiler optimisation is almost entirely local decisions, wheras place and route is essentially a global optimisation problem).

tails4e 6y ago
I guess my perspective comes from the other side, ASIC tools that do the same thing (synthesis, place and route, STA, simulation) are way, way worse. Design compiler was designed in the 90s, and while it has many advanced features, it's usability is incredibly poor. A million variables you never heard of, and each one tweaks its behaviour in weird and wonderful ways, and a GUI that still looks like its from the 90s. Costs 90k a seat to boot, but if you're doing ASIC design, it's one of the major tools you will use. And it just does the synthesis bit. Vivado does it all, and has seamless cross probing between each stage, right back to source code. It's usability to me is refreshing. I have found bugs, sure, but never a show stopper. It's free Verilog simulator (xsim) is better than any other free system Verilog simulator out there, and that's just one sub component of Vivado.
- rcxdude 6y ago
  oh yeah, by all accounts ASIC design tools are even worse. But from a software perspective FPGA tooling is still in the dark ages from most perspectives (and the frustrating thing is a lot of it wouldn't be very hard to do better).