I guess my perspective comes from the other side, ASIC tools that do the same thing (synthesis, place and route, STA, simulation) are way, way worse. Design com

I guess my perspective comes from the other side, ASIC tools that do the same thing (synthesis, place and route, STA, simulation) are way, way worse. Design compiler was designed in the 90s, and while it has many advanced features, it's usability is incredibly poor. A million variables you never heard of, and each one tweaks its behaviour in weird and wonderful ways, and a GUI that still looks like its from the 90s. Costs 90k a seat to boot, but if you're doing ASIC design, it's one of the major tools you will use. And it just does the synthesis bit. Vivado does it all, and has seamless cross probing between each stage, right back to source code. It's usability to me is refreshing. I have found bugs, sure, but never a show stopper. It's free Verilog simulator (xsim) is better than any other free system Verilog simulator out there, and that's just one sub component of Vivado.