menaerus

27 ms·

451.
by menaerus 1y ago
No, because optimizing compilers are free to elide the check. https://gcc.gnu.org/onlinedocs/gcc/Optimize-Options.html#ind...
452.
by menaerus 1y ago
It's a compile-time flag which is defined when libpthread is linked into the binary.
453.
by menaerus 1y ago
I mean, the base and turbo frequency are about the same on both parts, and the workload is very very simple. Case where TDP would matter is with the workload sucking up all the power budget of a whole chip in which case frequency would have
454.
by menaerus 1y ago
Data suggests that they are, and common sense too. And your point of reference is a little bit problematic since there's no code attached so it's hard for people to validate the measurements. Since you have been laser-focused on s
455.
by menaerus 1y ago
No VM, no container. I could check the asm later on but sqrtrec is likely "free" because it was optimized away, no fences in the code neither so this might be an artifact of different versions of gcc being used across two differen
456.
by menaerus 1y ago
I never heard of this and went to check in the source and it really does exist: https://codebrowser.dev/llvm/include/c++/11/ext/concurrence....
457.
by menaerus 1y ago
Interesting because on my machine I can reproduce the results. It's a pretty hefty 5.3GHz and recentish (Raptor Lake) Intel i7-13850HX CPU: ---------------------------------------------------------------------------- Benchmark
458.
by menaerus 1y ago
Benchmark is simple but I find it worthwhile because of the fact that (1) it is run across 15 different platforms (different CPUs, libc's) and results are pretty much reproducible, and (2) it is run through gbenchmark which has a mecha
459.
by menaerus 1y ago
Where is the state/registers written to then if not L1? I'm confused. What do you say about the measurements from https://gms.tf/on-the-costs-of-syscalls.html ? Table suggests that the cost is by a magnitude larger
460.
by menaerus 1y ago
I'm on my mobile. Store to L1 width is typically 32B and you're probably right that CPU will take advantage of it and pack as much registers as it can. This still means 4x store and 4x load for 16 registers. This is ~40 cycles. So
461.
by menaerus 1y ago
50ns on a 3GHz CPU core is ~150 cycles. Pushing and popping back the registers to L1 cache is 5-10 cycles each. With having to handle 16 general purpose registers on x86-64 this is already close to or even more than 150 cycles, no?
462.
by menaerus 1y ago
If it isn't a vDSO call, I think 50ns figure shouldn't be possible.
463.
by menaerus 1y ago
AI is already being used both by lawyers and doctors so I am not sure what's the point you're trying to make. All I tried to say with my comment is that technology is very worthwhile and that ones ignoring it will be the ones at t
464.
by menaerus 1y ago
> That sentiment will be the same for doctors, lawyers, etc., and personally, I won't put my life in the hands of any LLMs when it comes to finances, health, or personal well-being, for that matter. I mean, did you try it for those
465.
by menaerus 1y ago
> We are a tiny but prolific team in San Francisco (with a median typing speed of 120 wpm) I couldn't resist.
466.
by menaerus 1y ago
In HW?
467.
by menaerus 1y ago
Single core only @turbo-boost.
468.
by menaerus 1y ago
It's a transpiler that takes the x86-64 binary assembly and spits out the aarch64 assembly only on the first run AFAIK. This is then cached on storage for consecutive runs.
469.
by menaerus 1y ago
Hm, what I have seen so far is that pointers returned by system malloc are usually aligned either to 8-byte boundary (windows) or 16-byte boundary (linux). I think jemalloc interprets the C standard guarantees a bit differently and will ret
470.
by menaerus 1y ago
How about taking the advantage of max_align_t pointer alignment guarantees, which on x86-64 Linux (glibc) is 16-bytes? This would leave you with the 4 lowest bits to be used.
471.
by menaerus 1y ago
> We can't know if a generic path is valid at compile time. But we can at compile time ensure that we must acknowledge and make a choice for the invalid case. While a pragmatic choice, in reality it isn't very practical IMO. Mo
472.
by menaerus 1y ago
You said > With a standard library and culture built on exposing the edge cases at compile time. So, how exactly is "you need to acknowledge that the path may be invalid" from your example a compile-time trait? That's cert
473.
by menaerus 1y ago
Opaque types cannot be stack- or statically allocated.
474.
by menaerus 1y ago
Show me an example. I don't understand this marketing lingo.
475.
by menaerus 1y ago
DeepSeek team, which is also an HFT shop, also implemented their DFS - https://github.com/deepseek-ai/3FS
476.
by menaerus 1y ago
Yes, it can be implemented basically in any language that can hide the data members so I also see nothing special about it.
477.
by menaerus 1y ago
Two-character SIMD filtering improved performance significantly: ClickBench query Q20 sped up by 35% Other queries which perform substring matching saw an overall improvement of ~10% The geometric mean of all queries impr
478.
by menaerus 1y ago
I don't think it was an insult, at least it is not what I intended, but rather trying to make the fallacy in your response to my comment more explicit. I don't know of a better way, and I can't run circles around people in co
479.
by menaerus 1y ago
For most people this is a feature not a bug as you suggest. It may come across as PITA, and for many people will do, but as far as I am concerned, while also having experienced the pain of package managers in C++, this is the right way. In
480.
by menaerus 1y ago
> Not sure where you're getting L1 from. The folly comment doesn't mention it. True, it is what I assumed. Do you think they meant false-sharing on L2 level?

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