4 ms·
In HW?
by menaerus 1y ago
In HW?
- antonvs 1y agoNot OP, but I don’t think so. Rosetta inserts ARM barrier instructions in its generated code to emulate x86 memory ordering.
- timschmidt 1y agoYup! See here: https://www.sciencedirect.com/science/article/pii/S1383762124000390 https://www.sciencedirect.com/science/article/pii/S138376212...