dalance

8 ms·

1.
by dalance 2mo ago
Sorry. I have decided to stop making posts like this. I will try to delete this post if there is a way to do so.
2.
Official Package Registry of Veryl(veryl-lang.org)
2 points by dalance 2mo ago|2 comments
3.
Heliodor: An RVA23-Compliant Multicore Out-of-Order RISC-V Core in Veryl(veryl-lang.org)
2 points by dalance 3mo ago|0 comments
4.
Veryl Simulator: Performance Comparison with Verilator(veryl-lang.org)
3 points by dalance 4mo ago|0 comments
5.
Veryl 0.20.0: logic synthesis and type inference are supported(veryl-lang.org)
2 points by dalance 5mo ago|0 comments
6.
Veryl 0.16.4 – A Modern HDL as Alternative to SystemVerilog(veryl-lang.org)
3 points by dalance 1y ago|0 comments
7.
by dalance 1y ago
As the author of Veryl and an ASIC frontend engineer, I aim to enable smooth transitions from existing SystemVerilog projects, making it immediately applicable to ASIC projects. (In fact, it’s already being applied to an ASIC currently unde
8.
Veryl 0.16.0 – A Modern HDL as Alternative to SystemVerilog(veryl-lang.org)
3 points by dalance 1y ago|0 comments
9.
Veryl 0.14.0 – A Modern HDL as Alternative to SystemVerilog(veryl-lang.org)
2 points by dalance 2y ago|0 comments
10.
Rust Document Translation Project(rust-lang-translations.org)
1 points by dalance 2y ago|0 comments
11.
Verylup 0.1.2 – the official installer for Veryl(veryl-lang.org)
1 points by dalance 2y ago|0 comments
12.
Veryl 0.13.0 – A Modern HDL as Alternative to SystemVerilog(veryl-lang.org)
2 points by dalance 2y ago|0 comments
13.
Veryl 0.12.0 – A New Hardware Description Language(veryl-lang.org)
1 points by dalance 2y ago|0 comments
14.
Veryl v0.12.0: A New Hardware Description Language(github.com)
1 points by dalance 2y ago|0 comments
15.
by dalance 3y ago
Thank you for your information about Lola-2 HDL. I'll check it. As a verification engineer, I write large verification models by Rust, and connect them to SV testbench through DPI. The same usage can be done by Veryl. About Python, coc
16.
by dalance 3y ago
I'm focusing ASIC designers who write synthesizable SystemVerilog. So I choose language features to avoid mismatch between synthesis and simulation. Verification engineers is a second group. But verification features like SVA and UVM a
17.
by dalance 3y ago
I agree both issues. I experienced the whole design became to be broken by adding a trait in my Chisel work. When I want to change a timing path related a register, Chisel-ish sophisticated descriptions could't be used. I think SystemV
18.
by dalance 3y ago
I plan to introduce generics to enable module/interface/package as type parameter. But I'm not aiming Chisel like programability. I tried to use Chisel in a large codebase to judge it can be used as SystemVerilog alternative
19.
by dalance 3y ago
Hi, Im' developer of Veryl. So I'll try to write the answer to "why new HDL?". I use SystemVerilog from 10+ years ago, and developed many large ASICs. But development environment of SystemVerilog was poor than software d