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As the author of Veryl and an ASIC frontend engineer, I aim to enable smooth transitions from existing SystemVerilog projects, making it immediately applicable
by dalance 1y ago
As the author of Veryl and an ASIC frontend engineer, I aim to enable smooth transitions from existing SystemVerilog projects, making it immediately applicable to ASIC projects. (In fact, it’s already being applied to an ASIC currently under design.) I see languages like Spade and SUS as HDLs for a slightly more future-oriented.