I agree both issues. I experienced the whole design became to be broken by adding a trait in my Chisel work. When I want to change a timing path related a regis

I agree both issues. I experienced the whole design became to be broken by adding a trait in my Chisel work. When I want to change a timing path related a register, Chisel-ish sophisticated descriptions could't be used. I think SystemVerilog has sufficient function for ASIC development. So I think more efficient development can be achieved if there are modern development tools like real-time semantic checker through language server, build tool handling dependencies, and so on.