avianes

22 ms·

151.
by avianes 6y ago
On modern chips, we are not only "fusing out" faulty cores. We also put more memory cuts than necessary into the silicon and we fuse out the defective ones to increase the yield. You can look at Memory BISR (built-in-self-repair).
152.
by avianes 6y ago
Could you explain why you left ProtonMail?
153.
The SIMT microarchitecture from Nvidia GPUs explained (2017)(gpgpu-sim.org)
1 points by avianes 6y ago|0 comments
154.
by avianes 6y ago
I have thought about it a little more, and I think it's the right solution as well. From the first proposal the compiler can directly prepare the stack for the call. As in this example: https://godbolt.org/z/f17szP
155.
by avianes 6y ago
That's quite interesting. I see two possible implementations: - either the struct is replicated at the function call (not really efficient, but the semantics are straightforward); - either the struct is used to prepare directly the sta
156.
by avianes 6y ago
The cache-coherency must already ensure that. Memory mirroring conditions should include the permission to read (or write, depending on usage) the data cache-line.
157.
by avianes 6y ago
In order for memory mirroring to be enabled, the memory must probably be read first since its value must be used. The processor must then ask the cache controller to acquire the cache-line in a "no writer / multiple reader" m
158.
Intel 4004 Visual Transistor-level Simulation(youtube.com)
1 points by avianes 6y ago|0 comments
159.
by avianes 6y ago
There are probably several power domains in the chip and therefore several separate power supplies, which avoids the need to manage 15kW in a single spot. Edit: In the slides shared above [1] (page 16), it says "12x 4kW hot-swappable u
160.
by avianes 6y ago
I'm very skeptical about the paper's conclusions. the measurements show that they can generate bb of about 10~20 instructions (optimistic numbers as they measure an average of 5) which allows them to move up the branches of about
161.
by avianes 6y ago
> There are no bitmanip extensions in the core instruction set where it is needed. That's the whole idea of an extension. You may or may not include it depending on your needs. > And there are no bitmanip extensions in any existi
162.
by avianes 6y ago
> a = (x & c) | (y & ~c) > is a branch-free conditional assignment, and only works with c = 0 or ~0. Using this hack only makes sense if there is no "conditional move". But the bitmanip risc-v extension offers a &q
163.
by avianes 6y ago
> - have rotate instructions in the core set > - have popcount instructions in the core set There is the Bitmanip extension for that. Why it should be in the core ISA ? Microcontrollers don't always need it. The purpose of the ex
164.
by avianes 6y ago
> Too much color ends up overwhelming. I can find the red circle super quick because it's the only red thing in a sea of black and white. > But I like the idea of going beyond syntax. Maybe a way to get the best of both worlds wo
165.
by avianes 6y ago
> Actually the main reason you see things out of order on a modern CPU are core-local reasons, like store buffering, store forwarding, load buffering, delayed invalidation processing and out of order execution. yes, precisely, since the
166.
by avianes 6y ago
Cache invalidation is a sub-problem of cache coherency. But the cache coherency is not the consistency model. "seeing things in order" is a problem that arises even for uncached accesses. If multiprocessor systems have trouble see
167.
by avianes 6y ago
This particular vulnerabilities use x86 specific instructions such as CPUID (which provides information about the CPU version) to extract the content of a shared buffer which contains sensitive data in some cases. This instruction (CPUID) i
168.
by avianes 6y ago
> Entire memory bus as in entire access to any kind of shared memory (shared CPU caches, RAM, ...)? I guess this is the only solution for Intel (apart from an hardware fix) as one core doesn't have control over the loads of another
169.
by avianes 7y ago
> But fundamentally what these attacks enable are super old & well known, with multiple existing mechanisms that fulfill similar roles. It still has to be published. The article doesn't claim to break all the isolation mechanism
170.
by avianes 7y ago
> The "new" AMD attack depends on lack of already existing spectre mitigations. No, it's a misunderstanding to say that the flaw in the "Take A Way" whitepaper depends on a mechanism already patched. Attack scena
171.
by avianes 7y ago
The author does not claim that these attacks currently allow to break all processor securities. He just points out that two new side channels are possible by exploiting AMD optimizations then it demonstrates their feasibility on already kno
172.
by avianes 7y ago
It would be interesting to also compare the power consumption of the embedded ARM processor in USB-C chargers with the power consumption of AGC (Apollo 11 guidance computer).
173.
by avianes 7y ago
Yes, this is a RIDL variant called "L1D Eviction Sampling". Bolt the RIDL paper (Addendum 2 B [1]) and the CacheOut paper refer to the CVE-2020-0549: "L1D Eviction Sampling (L1Des) Leakage". But the CacheOut paper descri
174.
by avianes 7y ago
> (Implicit destination followed by mov is free, because of register renaming.) There is no need for an implicit destination register, just do it explicitly and you get the same result but without any magic and with more control. Registe
175.
by avianes 7y ago
> And RISC-V exposes its internals But your example shows no internal states exposure, it's just arithmetic to detect overflow. What are you trying to show ?
176.
by avianes 7y ago
No, as jleahy said, it cost a single instruction to transform 0 to 0b00..00 and 1 to 0b11..11 - SUB X, $0, X. And your proposal - using the zero register as a flag register - breaks way more micro-optimizations (like the simple ones describ
177.
by avianes 8y ago
The ThinkPad T480 can support up to 32GB of ram.
178.
by avianes 8y ago
> This avoids reading the same row over and over again Didn't you notice a huge drop in performance producing row-buffer conflicts over and over ?
179.
by avianes 8y ago
I mean, as long as your ECC is built directly into the silicon
180.
by avianes 8y ago
Hardware implementation does not mean that there is no timing side-channel. Compute ECC takes few cycles. To avoid timing side-channel, you must design hardware for this purpose.

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