4 ms·
Hardware implementation does not mean that there is no timing side-channel. Compute ECC takes few cycles. To avoid timing side-channel, you must design hardware
by avianes 8y ago
Hardware implementation does not mean that there is no timing side-channel. Compute ECC takes few cycles.
To avoid timing side-channel, you must design hardware for this purpose.
- kingosticks 8y agoYeh I realised afterwards that at these high clock speeds maybe they do need some extra cycles to do the correction. I don't see why you must do it in hardware to avoid timing side-channels. You just need to provide a constant latency i.e. The cpu ucode does some nops when correction is not necessary.
- avianes 8y agoI mean, as long as your ECC is built directly into the silicon
- kingosticks 8y agoIn that case you need to do the exact opposite i.e. avoid the obvious optimisation of returning data early if no correction is required.