avianes

11 ms·

91.
by avianes 5y ago
Yes, the definition matches. But that doesn't mean that the architecture and the micro-architecture used is similar. So.. Yes! We can say that these architectures are some kind of "vector processors", but it will be ambiguous
92.
by avianes 5y ago
The terminology "vector processor" refers to a completely different type of architecture. Using it for SIMT architecture would be confusing
93.
by avianes 5y ago
That term is "SIMT architecture." Modern GPUs (or GPGPUs) are based on the SIMT programming model that requires an SIMT architecture
94.
by avianes 5y ago
> There's nothing preventing you from using their compiler with other people's chips right now. Using an other ISA than x86 is something that prevents this compiler from being used for other chips. The intermediate representati
95.
by avianes 5y ago
RISC-V is not an open-source royalty-free Core design. It's an open-source royalty-free ISA. Using the RISC-V ISA is free, and that means being able to use all the tools developed for this ISA for free. It is still very attractive in t
96.
by avianes 5y ago
> I can forcefully bound the return value of count_nodes() to be no more than 1000. If I change the code to return a standard size_t type, like so… size_t count_nodes(const node* p) { size_t size = 0; while (p) {
97.
by avianes 5y ago
yes, that's why I put "in theory". But you're right, I should have written something like "with a simplistic perspective" instead.
98.
by avianes 5y ago
I struggled to understand that you compute score/TDP > Waiting for apple fanboys telling me something like "but TDP is not a good measure"... Not an Apple fan, but TDP is not even a measurement, it's a specification o
99.
by avianes 5y ago
> "But the assembler has the LI pseudoinstruction so it will properly do this calculation for you!". Right, so much for "nice assembly language": you need an actual smart macroassembler to write it. In x86 the mnemoni
100.
by avianes 5y ago
Hardware and Software have very different dynamics, therefore the comparison with POSIX is very weak. There is no way today to build competitive opensource hardware, and RISC-V is not about providing opensource hardware. With RISC-V (or any
101.
by avianes 5y ago
But that's not a problem at all. It still guarantees that a program compiled for RISC-V will run on this CPU. Moreover, they have no motivation to introduce too many non standard/proprietary extensions as it would require them to
102.
by avianes 5y ago
All Spectre/Meltdown attacks go through the same 3 steps in this order: 1) taking control over transient instruction execution 2) controlled transient instructions access a legal data (but illegal for us) 3) controlled transient instru
103.
by avianes 5y ago
There is an example of negative array indexing within standard lib implementations. Functions like isprint(int c), which checks whether c is a printable ASCII character, can take as input numbers between -128 and 127 or between 0 and 255. T
104.
by avianes 5y ago
Branch-Prediction and Value-Prediction are two similar fields but they are really different fields. When a branch prediction is wrong we have to change the execution path and therefore flush the executed instructions (on the wrong path). Wi
105.
by avianes 5y ago
In the field of high performance processor microarchitecture, one goal is to increase performance by executing a maximum number of instructions in parallel (increase IPC). For this purpose we identify dependencies between instructions. We i
106.
Using branch-prediction to perform software value-speculation(twitter.com)
3 points by avianes 5y ago|0 comments
107.
by avianes 5y ago
> In the end, you still have to trust the root domain, which means you still need to trust system firmware and the secure boot chain. You need to trust the hardware, and you also need the firmware. However, there is no need to trust the
108.
by avianes 5y ago
Thank you for your notes ! I saw a few months ago that there were more than 4 extensions in BitManip, but when I recently checked the github page only 4 were left. Is there a better source of information than the github page to know the dev
109.
by avianes 5y ago
> What you mean to say is that you do not personally understand the myriad uses where it makes an order of magnitude difference in performance You clearly misunderstand the concept of a modular ISA. RISC-V does not only target high perfo
110.
by avianes 5y ago
> Given he authored the D programming language, he is absolutely aware of the benefits of managing memory allocation, runtime checks for boundary overruns, etc etc... No doubt about that, but the proposal still does not address these iss
111.
by avianes 5y ago
The point is that the proposal does not fully address the issue. 1. It does not define the behavior when the bounds is exceeded. When using the '-Warray-bounds' option (with gcc) the compiler does its best to detect at compile tim
112.
by avianes 5y ago
> It should have been in the base instruction set. No, it should not. Popcount is not necessary for all the microcontrollers and it does not fully share its circuitry with the other instructions of the basic ISA. Popcount must be in an e
113.
by avianes 5y ago
That' s funny, you are posting this exact same message in every RISC-V news I read. > It is hard to understand how it could have been omitted. This has not been omitted at all. The spec of the bitmanip extension, which contains the
114.
by avianes 5y ago
> I invite everyone to read this article about how Wikipedia took several years to implement the "show preview when hovering a link" feature. But we are talking about Firefox not Wikipedia. I would be happy to read a full arti
115.
by avianes 6y ago
> If FPGAs were so good as processors, everybody would run them. FPGA are used to demo processors but then they end up in silicon because of integration, cost and power consumption. You're right, but that's precisely what they
116.
by avianes 6y ago
Not sure if the checks of all loads are done at instruction retirement, but yes they are done after the (speculative) execution of the load. We can also talk about the Store-to-Load Forwarding involving a partially check physical address, e
117.
by avianes 6y ago
Modern processors execute more than one instruction per cycle by executing several instructions in parallel on each core. In sequential code, it's common that some instructions are independent and can theoretically be executed in paral
118.
by avianes 6y ago
Be careful not to confuse ECC memory with ECC encryption. ECC memory = memory with Error-Correcting Code ECC encryption = Elliptic Curve Cryptography
119.
by avianes 6y ago
What you say is wrong in many ways. You are talking about forking the project even though the spec is not yet finished and the project is open source and open to participation. Instead of forking, just let the RISC-V team know what the prob
120.
by avianes 6y ago
> Nothing like it can be done for an x86 cpu. The way modern x86 handles this is typically with a uop cache. But this costs a lot of power, area and only provides full decode width for a relatively small pool of insns -- 4k on modern Zen

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