> Some critique may come from wrong assumptions, but being critical is not just bashing Focusing criticism only on this architecture, producing criticism witho

> Some critique may come from wrong assumptions, but being critical is not just bashing Focusing criticism only on this architecture, producing criticism without any solid argument, putting aside all the positive aspects, criticism when you clearly lack of expertise, sending similar criticisms in several conversations when already debunked on multiple occasions.. This is really systematic on discussion about RISC-V. That's what I call bashing, I cannot call that legitimate, correct or constructive criticism. > The ISA specification was released in 2011! In one year! [...] But if you look at the changes and skip anything that isn't just renaming / reordering / clarifying things, it always fits on half a page. I encourage anyone to open the original document published in 2011 [1] and compare it with current RISC-V specification documents [2]. There is very little left from the 3 month student work, it mainly remains the philosophy which is probably highly influenced by project supervisors. Moreover, it mainly consists of the basic RISC-V ISA which is indeed designed to be simple and minimalist, whereas the current RISC-V full spec. consists of a multitude of extensions. At this stage your statement and the statement from the email is not just exaggerated, it is pure misinformation. > Not an ISA designed by industry experts for high performance cores Okay, the industry wasn't involved as much as today in the beginning. But RISC-V is really the product of experts in the field of high performance architectures [1] https://www2.eecs.berkeley.edu/Pubs/TechRpts/2011/EECS-2011-62.pdf https://www2.eecs.berkeley.edu/Pubs/TechRpts/2011/EECS-2011-... [2] https://riscv.org/technical/specifications/ https://riscv.org/technical/specifications/