You are right but RISC-V variable instruction size is indeed a good trade-off. Unlike x86 where instructions can range from 1 up to 15 byte, current RISC-V ISA

You are right but RISC-V variable instruction size is indeed a good trade-off. Unlike x86 where instructions can range from 1 up to 15 byte, current RISC-V ISA only has 2 instruction sizes. Today x86 decoding is limiting because we want to decode more than ~4 instructions each cycle, for RISC-V to cause same decoding difficulty it would probably be required to decode more than ~20 instructions each cycle