asb

21 ms·

181.
by asb 12y ago
Building on this - what happened to Mibbit? Axod used to post on HN regularly with really impressive load and growth stats https://news.ycombinator.com/user?id=axod . It seems that after Freenode blocked it, progress rather
182.
by asb 12y ago
While we're sharing GSoC project ideas, I'd like to highlight the list we have at lowRISC - covering a wide range of languages and just about every part of the hardware/software stack. http://www.lowrisc.org/d
183.
by asb 12y ago
It's a shame RMS made no reference to the current activity around RISC-V http://riscv.org/ a freely implementable instruction set architecture with BSD-licensed reference implementation. At lowRISC http://lo
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Google Summer of Code now open for student applications(google-opensource.blogspot.com)
3 points by asb 12y ago|0 comments
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Mentoring Organizations for Google Summer of Code 2015 Announced(google-opensource.blogspot.com)
2 points by asb 12y ago|0 comments
186.
by asb 12y ago
If you want to keep up to date on developments in LLVM, Clang and related projects between releases, you may be interested in my LLVM Weekly newsletter http://llvmweekly.org/
187.
by asb 12y ago
It would be difficult in the near term. With lowRISC ( http://www.lowrisc.org ), some of us are working towards a complete open source SoC (i.e. the RTL is available under a permissive open source license). Although our longer ter
188.
by asb 12y ago
You may also be interested in a project a number of us have been working called lowRISC, aiming to produce a fully open-source SoC in volume using the RISC-V instruction set architecture. http://www.lowrisc.org/ I'm gi
189.
by asb 12y ago
Presumably the feature that is being discontinued is for authorising payments that aren't actually taken until later in the future. I could certainly imagine this has a disproportionately high support cost.
190.
by asb 12y ago
Check out the rather hidden http://movies.netflix.com/WiRecentAdditions
191.
by asb 12y ago
Hygienic macros for Go (i.e. an equivalent of sweet.js http://sweetjs.org/ ) would be very interesting.
192.
by asb 12y ago
Adam Schwartz's Magic of CSS has a nice trick for getting the same effect without needing a custom font. See it in action at http://adamschwartz.co/magic-of-css/potions/two-pane-app/ The relevant CSS is
193.
by asb 12y ago
About 2-3 hours. In contrast to some other newsletters, I'm actively trying to summarise upstream development and development discussion rather than just linking to related projects. This involves reading all the mailing list posts and
194.
by asb 12y ago
I thought people may be interested in this update. I started LLVM Weekly on the first Monday of 2014, and have somehow managed to get it sent out every Monday since. As of today's issue, I've managed to complete it for every Monda
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My weekly newsletter about LLVM/Clang has been running for one year(llvmweekly.org)
85 points by asb 12y ago|10 comments
196.
by asb 12y ago
If you're at 31C3 and interested in an open-to-the-RTL platform, which (yes, I'm biased) seems the logical next step, bunnie is leading a discussion on lowRISC tomorrow (Monday) at 2pm. https://events.ccc.de/congre
197.
by asb 12y ago
This is actually one of the things we're looking at with the open-source lowRISC project. Moving aspects of the I/O system to RISC-V cores to enable you to implement SPI, I2C, I2S etc and other custom protocols in software. http:
198.
by asb 12y ago
HDL (hardware description language) is an interesting case. With lowRISC ( http://www.lowrisc.org ) we are working to produce an open source SoC using RISC-V. The parts of the chip described in high level HDL (e.g. the main '
199.
by asb 12y ago
lowRISC is a project to produce a fully open-source SoC using the RISC-V instruction set architecture, intending to reach volume production. Please do ask away if you have any questions.
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Show HN: Tagged memory and minion cores in the lowRISC SoC(lowrisc.org)
9 points by asb 12y ago|1 comments
201.
by asb 12y ago
I am personally very sympathetic to concerns about the efficiency of overflow checking. There has been some discussion of this on the riscv-hw mailing list, e.g. https://lists.riscv.org/lists/arc/hw-dev/2014-0
202.
by asb 12y ago
The 2-4 main cores will be derived from the UC Berkeley Rocket core generator https://github.com/ucb-bar/rocket . Currently this is single issue, in-order though it is designed to be a dual-issue in-order core (i.e. sup
203.
by asb 12y ago
Yes, the core team is based in Cambridge, UK. However we do intend to be a truly open-source project, with an open and distributed development process which would involve arbitrarily geographically distributed third-party contributors.
204.
by asb 12y ago
You're asking for a picture of a particular RISC-V implementation and its chosen microarchitecture. The RISC-V ISA has a range of different implementations each hitting different points in the design space and different trade-offs in t
205.
by asb 12y ago
Thanks for your interest, we're hoping to share more very soon.
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by asb 12y ago
We at lowRISC intend to produce in volume at 40nm or 28nm. http://www.lowrisc.org/
207.
by asb 12y ago
I do get that, but the distinction I'm trying to make between a feature like this and HKT is that you would expect changes in this area to impact practically every Rust program in existence, while the same is not necessarily true for H
208.
by asb 12y ago
I do wonder if Rust 1.0 is being branched just a little bit too early. I understand that you have to draw a line in the sand somewhere, and the rolling release model means new features can be rolled out quickly. On the other hand, I'm
209.
by asb 12y ago
Runabove (one of OVH's brands) offers very compelling pricing for object storage and transfer. $0.01/GB for transfer. It seems very tempting to store to both AWS and Runabove, keeping AWS in backup in case Runabove has issues.
210.
by asb 12y ago
Thanks for the answer. Another quick question. One of the limitations of parallela is the offchip memory bandwidth. Will you be integrating a third party phy?

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