4 ms·

You may also be interested in a project a number of us have been working called lowRISC, aiming to produce a fully open-source SoC in volume using the RISC-V in

by asb 12y ago

You may also be interested in a project a number of us have been working called lowRISC, aiming to produce a fully open-source SoC in volume using the RISC-V instruction set architecture. http://www.lowrisc.org/ http://www.lowrisc.org/ I'm giving a main track talk on it at FOSDEM next weekend: https://fosdem.org/2015/schedule/event/lowrisc/ https://fosdem.org/2015/schedule/event/lowrisc/ so say hi if you're there. My speaker interview gives more background on the project and our motivations https://fosdem.org/2015/interviews/2015-alex-bradbury/ https://fosdem.org/2015/interviews/2015-alex-bradbury/

aidenn0 12y ago
I haven't looked at RISC-V much; a quick glance at the ISA spec makes me think it has 32 GPRs? That is nice to see, as with Power slowly fading and Sparc essentially dead, we are stuck with the somewhat more constrained x86-64 and ARM. SBCL, for example, uses 2 stacks in its precise GC, as it will use one stack for unboxed integers and calling out to C, and another for lisp objects, which should be the roots for the GC; on x86-64 it uses a conservative GC for this reason (on ARM they implemented the precise one, but seem to be losing significant performace due to register pressure). In general 16 registers seems to be "just barely enough" most of the time, which translates to "super painful" the few times you could use more.
- hga 12y ago
  Yep, it's got 32 GPRs, with #0 hardwired to the constant 0. And the lowRISC project is looking into adding two tag bits with a focus on practical security for languages like C, but with the ability to use them for things like GC. Largest nits I see about the RISC-V ISA is no support for integer math error checking aside from divide by zero (a New Jersey design), and per a slide set I found for the January workshop, the work in progress 64 bit VMM mode will only support 43 bits of address space, i.e. "only" 8 TiB, vs. e.g. the 256 TiB of x86-64. Which of course is rather a lot, but I find it uncomfortably close to the DRAM you can put on current systems with Intel CPUs; I've watched this game way too many time in my career.
  - aidenn0 12y ago
    The 43-bits; is that a limitation on physical or virtual addresses? Also, don't forget that DRAM isn't the only consumer of physical address space.
    - hga 12y ago
      It's from a slide set, the first draft of RISC-V's "Privileged ISA Specification" is still being worked on before initial release, which is supposed to happen RSN. I'm assuming it's the virtual address space limit.

by asb 12y ago

aidenn0 12y ago

I haven't looked at RISC-V much; a quick glance at the ISA spec makes me think it has 32 GPRs? That is nice to see, as with Power slowly fading and Sparc essentially dead, we are stuck with the somewhat more constrained x86-64 and ARM. SBCL, for example, uses 2 stacks in its precise GC, as it will use one stack for unboxed integers and calling out to C, and another for lisp objects, which should be the roots for the GC; on x86-64 it uses a conservative GC for this reason (on ARM they implemented the precise one, but seem to be losing significant performace due to register pressure). In general 16 registers seems to be "just barely enough" most of the time, which translates to "super painful" the few times you could use more.

hga 12y ago
Yep, it's got 32 GPRs, with #0 hardwired to the constant 0. And the lowRISC project is looking into adding two tag bits with a focus on practical security for languages like C, but with the ability to use them for things like GC. Largest nits I see about the RISC-V ISA is no support for integer math error checking aside from divide by zero (a New Jersey design), and per a slide set I found for the January workshop, the work in progress 64 bit VMM mode will only support 43 bits of address space, i.e. "only" 8 TiB, vs. e.g. the 256 TiB of x86-64. Which of course is rather a lot, but I find it uncomfortably close to the DRAM you can put on current systems with Intel CPUs; I've watched this game way too many time in my career.
- aidenn0 12y ago
  The 43-bits; is that a limitation on physical or virtual addresses? Also, don't forget that DRAM isn't the only consumer of physical address space.
  - hga 12y ago
    It's from a slide set, the first draft of RISC-V's "Privileged ISA Specification" is still being worked on before initial release, which is supposed to happen RSN. I'm assuming it's the virtual address space limit.