HDL (hardware description language) is an interesting case. With lowRISC (http://www.lowrisc.org http://www.lowrisc.org) we are working to produce an open sourc

HDL (hardware description language) is an interesting case. With lowRISC (http://www.lowrisc.org http://www.lowrisc.org) we are working to produce an open source SoC using RISC-V. The parts of the chip described in high level HDL (e.g. the main 'Rocket' core) do not have the same issues described in this document. Assuming you have access to appropriate tools and a design kit for the technology node you want to target (which can be expensive and/or difficult) then for the most part, if it synthesises and passes the design rule checks you can be fairly sure it will work. Where this completely falls down is for the more analog aspects of the chip, such as the memory PHY (physical interface). This is typically specific to the fab process being used and really can not be verified and reasoned about in such a straight-forward way. People obviously do SPICE simulations and the like, but that only gets you so far.