adapteva

14 ms·

121.
by adapteva 10y ago
Design symmetry and regularity was the key. Harder to achieve that with a heterogeneous architecture.
122.
by adapteva 10y ago
Emacs! Here's one from ARL: http://www.ieee-hpec.org/2015/finalpapers_site/17_87-Impleme...
123.
by adapteva 10y ago
Yes, we are leaving 2X on the table in terms of peak frequency compared to well staffed chipzilla teams. Not ideal, but we have a big enough of a lead in terms of architecture that it kind of works.
124.
by adapteva 10y ago
Hours were over a 12 month period, but yes...the pace was relentless. All ambitious projects, including many kickstarer projects get done because creators end up working for free for essentially thousands of hours. In this case, we were on
125.
by adapteva 10y ago
Documents: http://adapteva.com/docs/epiphany_arch_refcard.pdf http://adapteva.com/docs/epiphany_arch_ref.pdf Not competitors yet. They have awesome silicon in the field, we just taped out...
126.
by adapteva 10y ago
Not going to happen in the near term. There is no way to meet the price point needed to compete in the low cost SBC market with the Epiphany-V. Believe it or not, the $99 Parallella was priced too high to reach mass adoption.
127.
by adapteva 10y ago
It comes back to the programming model. Synchronization is all explicit. See publication list. Includes work on MPI, BSP, OpenMP, OpenCL, and OpenSHMEM. The work from US army research labs on OpenSHMEM is especially promising. It's a P
128.
by adapteva 10y ago
You need think of it as aggregate memory, not as per core memory to use if effectively. Are you aware of a chip with more than 64MB of on chip RAM?
129.
by adapteva 10y ago
Hah! You thought you would get us with that one.:-) Here is the link to the Erlang OTP developed at Uppsala University for Epiphany. https://github.com/margnus1/otp
130.
by adapteva 10y ago
That's an older paper, but yes there have been more than one independent study showing 25x boost in terms of energy efficiency. See Ericsson FFT paper, OpenWall bcrypt paper, and others at parallella.org/publications.
131.
by adapteva 10y ago
In general it was built for math and signal processing (broad field). Within those fields, more specifically it was designed initially for real time signal processing (image analysis, communication, decryption). Turns out that makes it a pr
132.
by adapteva 10y ago
I am here, if anyone has questions. AMA! Andreas
133.
by adapteva 10y ago
Agree with you. Taping out chips is still like going to the dentist for a root canal. Still, we may have to disagree regarding the absolute numbers. For every one of our chips so far, we made RTL changes less than 24 hours before tapeout. (
134.
by adapteva 10y ago
Until 2011, all of our tapeouts were shuttles. (for our initial market the per die cost was fine). You get 50 dies/wafer on a shuttle run and can order a lot of wafers...with a theoretical per wafer price of $5000 that would mean $100
135.
by adapteva 10y ago
I provided ranges in the paper. To focus in further, you will need to get actual quotes from vendors. This is because the price is completely opaque and depends on circumstances. http://www.adapteva.com/andreas-blog/sem
136.
by adapteva 10y ago
imho, the only reason to go to 14nm and below is if you are pushing the envelope in terms of performance (HPC) or integration (smartphone). Everything else can probably stay at 28nm or above and be combined with 14-7nm using 2.5D or 3D pack
137.
by adapteva 10y ago
We can't tell you the detailed costs because this would violate our NDAs, but until our 2011 28nm tapeout, we had raised less than $2.5M in capital and taped out 4 chips at 65 and 28nm. There is no mystery here. EDA costs, tapeouts, en
138.
by adapteva 10y ago
Not sure I see what the purpose of taping out Leon at 180nm? Is it just to have an open source CPU? Hardware is only useful if it's competitive.
139.
by adapteva 10y ago
Simply not true as a general statement. There is a completely automated path from Verilog to GDS through modern EDA tools. While the back end complexity has increased, the folks at Synopsys, Cadence, Mentor have solved all of the problems f
140.
by adapteva 10y ago
Agree that there will be less designs that need the advancing nodes (the number of apps needing 1B transistors per chip is limited), but there will be plenty of opportunities at the system level that warrant the $10M type investment needed.
141.
by adapteva 10y ago
Put simply "stuff". Take a look at Fred Brooks, mythical man month if you haven't ready it already. The projects that cost $250M will have over 1,000 engineers involved. Running a tightly coupled engineering project of that s
142.
by adapteva 10y ago
If the cost of chip back-end is increasing exponentially from 65nm to 28nm to 14nm you are doing it wrong. (it's that simple). Since 0.25um, I have heard doom and gloom about how difficult "the next node" will be. So far it h
143.
by adapteva 10y ago
Yosefk, thanks for pitching in and fighting the complete bs that gets flung around regarding chip design costs. Some of these projections are just ludicrous, clearly made by people who are not currently involved in chip design. For argument
144.
by adapteva 10y ago
Nonsense. It's not open at any level by normal definitions (although some of the software is open source). The Raspberry Pi is a wonderful thing. It's cheap and it works great...but it's not open.
145.
Dude, Where's My Community?(adapteva.com)
2 points by adapteva 11y ago|0 comments
146.
by adapteva 11y ago
Amen!
147.
by adapteva 11y ago
I had the pleasure of meeting Professor Ranjit Manohar of Cornell a few years ago. He was the founder of Achronix, an FPGA startup. He said: -only 2% of the standard FPGA fabric does useful work.. & -the really expensive part to develop
148.
by adapteva 11y ago
You can get lattice FPGAs for a few dollars each from distributors. Zynq's in volume are reportedly as $15/each. Tools are free. If cost is the main concern, then how low do you need to go? An open FPGA arhitecture is a good thing
149.
by adapteva 11y ago
Before answering...what do you see as the problem today and what is your goal?
150.
by adapteva 11y ago
There is no typical...but here are some guidelines 1.2x (companies are either ultra efficient, copycats, suicidal, or dumping) 2x (US companies shipping volume, healthy) 4x (goal for FPGA companies and mixed signal niche) 10x (goal for comp

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