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If the cost of chip back-end is increasing exponentially from 65nm to 28nm to 14nm you are doing it wrong. (it's that simple). Since 0.25um, I have heard doom a
by adapteva 10y ago
If the cost of chip back-end is increasing exponentially from 65nm to 28nm to 14nm you are doing it wrong. (it's that simple). Since 0.25um, I have heard doom and gloom about how difficult "the next node" will be. So far it hasn't happened. If it does, I do agree that it's game over. So far the EDA companies and foundries have always come through.
- nickpsecurity 10y agoIt was that difficult. In my anti-subversion and OSS HW research, I've been collecting papers on EDA techniques and issues going back to the beginning so teams can build replacements for commercial tools over time. The reason it's not doom and gloom for the ASIC developer is that CompSci, EDA startups, and Big Three threw so many PhD's worth of thinking at each set of problems it isn't even funny. Talk about conquering chaos with human ingenuity every time a node shrinks. As you said, the EDA companies and foundries always came through. It was hard work, though. Work OSS will have to duplicate at least on EDA side.