3 ms·

Yosefk, thanks for pitching in and fighting the complete bs that gets flung around regarding chip design costs. Some of these projections are just ludicrous, cl

Yosefk, thanks for pitching in and fighting the complete bs that gets flung around regarding chip design costs. Some of these projections are just ludicrous, clearly made by people who are not currently involved in chip design. For argument's sake, let's pin the tapeout cost at $5M and EDA costs at $1M. Everything else is engineering. The reason these projects are expensive is that the chips are complex (because the have 10B transistors!). It has nothing to do with technology scaling (except for the fact that smaller nodes lets you integrate more transistors). I can design a memory chip (with repeating structures) in any node for almost nothing (..besides the tapeout cost). If they would have costs have escalated from $50K at to $5M at 14nm, that would be reasonable. The $250M number is utter nonsense.... Some more background: http://www.adapteva.com/andreas-blog/semiconductor-economics-101/ http://www.adapteva.com/andreas-blog/semiconductor-economics...

nickpsecurity 10y ago
The other comment to yosefk is mine citing your Lean Fabless article to contradict the point you just made slightly. Feel free to clarify on that if I'm misinterpreting something. Yet again, your next link supports "ludicrous" prices if it's a complex, full-featured SOC along lines of Apple products. Perhaps they should put qualifiers in these articles to be clear they're talking about high-end stuff with big numbers of parts and engineering required. If they even know what they're talking about. Yet, two of your articles suggest me doing a Snapdragon or something without buying third-party I.P. or RTL could easily cost the numbers in the article on 28nm. Or the other nm. Intended audience of those big nodes will also mostly be companies making stuff like that where they can afford development costs. Do shuttleruns even exist for 16/14nm?

nickpsecurity 10y ago

The other comment to yosefk is mine citing your Lean Fabless article to contradict the point you just made slightly. Feel free to clarify on that if I'm misinterpreting something. Yet again, your next link supports "ludicrous" prices if it's a complex, full-featured SOC along lines of Apple products. Perhaps they should put qualifiers in these articles to be clear they're talking about high-end stuff with big numbers of parts and engineering required. If they even know what they're talking about. Yet, two of your articles suggest me doing a Snapdragon or something without buying third-party I.P. or RTL could easily cost the numbers in the article on 28nm. Or the other nm. Intended audience of those big nodes will also mostly be companies making stuff like that where they can afford development costs. Do shuttleruns even exist for 16/14nm?