adapteva

38 ms·

91.
by adapteva 10y ago
Thanks for sharing your painful lesson. I feel your pain brother...I am still working on KS debt created 4 years ago:-( Don't EVER let the haters get you down. If you you are shipping products that people enjoy, you did not fail! http
92.
by adapteva 10y ago
Modern SOCs might have 100 complex blocks. We had 3 simple RTL blocks (9 hard macros). Top level communication approach was "correct by construction". Nothing is for free.
93.
by adapteva 10y ago
For Epiphany: GCC upstream already, working on GDB upstreaming. THere is no linux, qemu,uboot For Parallella: Linux upstream, uboot might be as well? Runs Debian, Ubuntu, etc https://github.com/adapteva
94.
by adapteva 10y ago
Sure...but probably not with all cores running full throttle. Would need to build an appropriate board.
95.
by adapteva 10y ago
Larger FPGA support 64-bits with custom memory controllers.
96.
by adapteva 10y ago
Impossible to characterize without high volume silicon or accurate yield models. We can say that historically, most failures are in SRAM cells and they are limited to a few bits (core still works!) and that in general only one out of N core
97.
by adapteva 10y ago
We are quite happy with our GCC port so LLVM hasn't been a priority. If anyone wants to take over the port, please do! We could give financial assistance for getting it completed, but the budget would be modest.
98.
by adapteva 10y ago
Up to 1 petabyte supported theoretically through FPGA interfaces. We can't disclose MPW costs. Chip was funded by DARPA. For standard MPW costs, check with MOSIS. https://www.mosis.com/
99.
by adapteva 10y ago
PAPER: https://www.parallella.org/wp-content/uploads/2016/10/e5_102... (access until we resolve the hosting issues, wordpress completely hosed...)
100.
by adapteva 10y ago
External RAM, up to 1 Petabyte would be connected through an external FPGA, containing an epiphany link, some glue logic, and a memory controller.
101.
by adapteva 10y ago
In modern DSP chips programmers have to contend with: VLIW, SIMD, pipelines, caches, and multicore. In Epiphany, the programmers are challenged by the manycore and an SRAM size cliff (so 0 or 1 in terms of pain). It depends...but I persona
102.
by adapteva 10y ago
No ECC on chip, but we do have column redundancy. We are pushing the envelope in terms of SEUs, making an assumption that the right programming model and run time will be able to compensate for high soft error rates. It's a contentious
103.
by adapteva 10y ago
You have to look at all the numbers (I/O, on-chip memory, flops, threads) and see if the architecture fits your problem. Some algorithms like matrix matrix multiplication are FLOPS bounds. It's rare to see a HPC architecture (don&
104.
by adapteva 10y ago
The issue is not bandwidth, it's the system cost. The chip has 1024 IO pins. (more than enough for MANY 10Gb nics...)
105.
by adapteva 10y ago
Some parallel algorithms will scale to bigger (more parallel) chips the way binary programs got more performance with clock higher frequencies. That's the holy grail..
106.
by adapteva 10y ago
I know...it's painful, we honestly weren't expecting this. Here are direct links if you are in a rush: Amazon: https://www.amazon.com/Adapteva/b/ref=bl_dp_s_web_9360745011... Digikey: http://w
107.
by adapteva 10y ago
:-) Thanks for making me laugh :-)
108.
by adapteva 10y ago
The chip is about the same size as the Apple A10, so in terms of silicon area it's in the consumer domain, but price will only come down to consumer levels if shipments get into millions of units. Big companies take a leap of faith and
109.
by adapteva 10y ago
It would be a BIG mistake to assume 1024 working cores. If you want to scale your software you should take a look Google/Erlang and others. Not reasonable to demand perfection at 16nm and below... Not saying we won't have chips wi
110.
by adapteva 10y ago
Sure, there will be evaluation boards, they just won't be generally available at digikey and won't cost $99. More information about custom ISA will be disclosed once we have silicon back.
111.
by adapteva 10y ago
HW design is not that different from SW design. Comp table below: HW SW Verilog --> C/Java/etc EDA --> GCC/LLVM GDS --> Binary (elf) The GDS is completely tied up in NDAs due to the foundry. The
112.
by adapteva 10y ago
Thanks for articulating. As you know, there is no right answer as it depends on workload. Now if we could only build a specific chip for every application domain....
113.
by adapteva 10y ago
Well, the Parallella has shipped to over 10,000 people and it still selling at Amazon an DK, so no the dream is not dashed in any way. The number of publications and frameworks around Parallella is growing every month... No reason to drive
114.
by adapteva 10y ago
Yes, you can call it scratchpad or sram. The point is that there is no hardware caching. The local SRAM is split into 4 separate banks so it is "effectively" 4 ported. DRAM controllers is up to the system designer. This is handled
115.
by adapteva 10y ago
I'll pass for now...Gaisler is in the business of consulting, we survive by building products. I am happy to release sources, but it's completely up to the EDA company. [edit: was thinking of the wrong Gaisler, still will pass]
116.
by adapteva 10y ago
Agree, but people have all kinds of pre-conceived notions about co-processors so let's clarify some things: e5 can't self-boot, doesn't have virtual memory management, and doesn't have hardware caching, but otherwise the
117.
by adapteva 10y ago
Good data! That puts e5 in good company with some big-iron heavies.
118.
by adapteva 10y ago
I have two excuses for why RISC-V didn't make it it. My February RISC-V post stated that we will use RISC-V in our next chip. We were already under contract for this chip so I was referring to the next chip from now. I had hopes of sne
119.
by adapteva 10y ago
This is actually a cut down erlang otp running on the Epiphany cores. It's not ready for production, but it's interesting research. See the README.
120.
by adapteva 10y ago
Paper stated that 500MHz number was arbitrary (had to fill in something for people to compare to). Agree that 500MHz with 16nm FinFet is ridiculously slow. We are not disclosing actual performance numbers until silicon returns in 4-5 months

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