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It would be a BIG mistake to assume 1024 working cores. If you want to scale your software you should take a look Google/Erlang and others. Not reasonable to de
by adapteva 10y ago
It would be a BIG mistake to assume 1024 working cores. If you want to scale your software you should take a look Google/Erlang and others. Not reasonable to demand perfection at 16nm and below...
Not saying we won't have chips with all cores working, just saying you shouldn't count on it.
- vardump 10y agoSo what can we count on? In a tile based CPU error topology matters. A string of broken cores or a broken core at the edges is likely worse than a broken core with all 4 (or 8?) neighbors working.
- adapteva 10y agoImpossible to characterize without high volume silicon or accurate yield models. We can say that historically, most failures are in SRAM cells and they are limited to a few bits (core still works!) and that in general only one out of N cores will fail. For arguments sake, let's assume the while network always works, but 1 CPU may be broken. (this is what needs to be confirmed later). Does that help?
- vardump 10y agoYes, that helps. It might be easier to work around broken SRAM bits than just skipping a whole core. That way you could always have same pipeline layout and not need to compute it dynamically.