adapteva

9 ms·

61.
by adapteva 3y ago
As a summary, the last 50 years has achieved smaller, cheaper, faster through monolithic integration Moore's Law). Cost and complexity of design and manufacturing is now making that approach impractical. Disaggregated design and manuf
62.
U.S. focuses on invigorating ‘chiplets’ to stay cutting-edge in tech(nytimes.com)
85 points by adapteva 3y ago|48 comments
63.
by adapteva 4y ago
Whiteboarding stuff in my office at DARPA with Ivan Sutherland is a memory I will treasure always. One of the original giants.
64.
by adapteva 4y ago
From personal experience it's at least 1%. I had a Kickstarter project 10 years ago that had approx 6,000 supporters and 50 were simply awful human beings. Everyone else was ok. Anonymity brings out the worst in some people.
65.
by adapteva 4y ago
Here's a compiled list of most of them. https://github.com/aolofsson/awesome-semiconductor-startups
66.
by adapteva 4y ago
Seems like people are interpreting whatever they want from the original chart by Raja Koduri at the VLSI symposium...plotted with absolute numbers you see that EE enrollment is pretty flat. What has happened is that the number of CS majors
67.
by adapteva 4y ago
I find it kind of weird how many people were offended by our use of the term, supercomputing. The actual specs were on the front page of the kickstarter from day one. Not sure what people were expecting from a $100 SBC? Kind of interesting
68.
by adapteva 4y ago
Hey...this was just me sharing a list of people who have done great work in open source...I don't see why you have to drag Parallella into this...still since you brought it up, Parallella was shipped to 10K customers and used in 200 re
69.
Making open source hardware design a reality(github.com)
138 points by adapteva 4y ago|36 comments
70.
by adapteva 4y ago
Going back to the original H&P texts and RISC philosophy, there is a claim that auto-increment addressing modes is too expensive due to the extra port in the RF + scheduling complexity. For an instruction set that should support embedde
71.
by adapteva 4y ago
That sounds about right. Pricing varies by state and plan, but at 5-6 people you get to $2-3K / month.
72.
by adapteva 4y ago
Family plan health insurance premiums on open market is $33K/year in New England (US). With group plans that goes down to $28K/year. A full time employee at $15/hr is $30k/year. The US healthcare system is fundamentally
73.
by adapteva 5y ago
Too much focus on ARM OR RISC-V. The processor space is incredibly diverse. There are tons of embedded applications that don't require massive software ecosystem. The tenslica, arc, ceva ISAs have all shipped in the billions sitting ne
74.
by adapteva 5y ago
If by the alternative you are referring to VPR, you are wrong. There are both public and non-public FPGA tool chains based on modified versions of VPR (and some of them are far more complex than what is currently handled by nextpnr).
75.
by adapteva 5y ago
No, it it is not a competetitor to openroad. It's more like a build system, like how make sits on top of llvm. Openroad is one of the tools under the hood.
76.
by adapteva 5y ago
Thanks for reading the docs! The only open manufacturable PDK is skywater 130, I wish there were more. Flow supports other commercial PDKs but for obvious reasons we can't publish those.
77.
by adapteva 5y ago
Expressing a complex project succinctly enough that all of HN will get it within 5sec is an np hard problem...here are the full docs. https://docs.siliconcompiler.com/en/latest/
78.
by adapteva 5y ago
Authore here. Python is for the build system. Plug in any front end you want. If you want to turn it into silicon, you will need to go through commercial tools which interface through proprietary tcl. How would you solve that problem? We so
79.
Compiling code into silicon(siliconcompiler.com)
134 points by adapteva 5y ago|63 comments
80.
by adapteva 5y ago
Over 200 comments and not a single benchmark comparison, if only there was some way to settle this argument...sigh.
81.
by adapteva 5y ago
Zero ASIC | Software Director, Analog Designer, Physical Designer | Boston or Remote (US) | Full-time | https://www.zeroasic.com/careers Zero ASIC is an early stage Boston based startup working to remove barriers to silicon
82.
by adapteva 5y ago
Happy to! Looks like the website broke during updates. The bios used to be there. Hopefully it will be fixed soon. Soon...
83.
by adapteva 5y ago
Still early days, but I disagree with some of your assertions. Seems to be a bit of an echo chamber in osh these days... The effort was not created in vacuum. -The skywater effort sits on top of darpa's openroad (I am currently on the
84.
by adapteva 7y ago
Let’s not forget the legendary Mensen Ernst. He raced against horses (and won?) in the 1700’s https://en.m.wikipedia.org/wiki/Mensen_Ernst
85.
by adapteva 7y ago
Not sure what you are referring to, but the majority of DARPA’s recent $110M investment in silicon design tools and opens source IP is dedicated to analog design.
86.
Darpa invests $100M in a silicon compiler(eetimes.com)
415 points by adapteva 8y ago|257 comments
87.
Funding a Revolution: Government Support for Computing Research (1999)(nap.edu)
1 points by adapteva 8y ago|0 comments
88.
by adapteva 9y ago
Working on it... https://www.fbo.gov/spg/ODA/DARPA/CMO/HR001117S0054/listing....
89.
by adapteva 9y ago
Touche!
90.
How to build a million core RISC processor(parallella.org)
3 points by adapteva 10y ago|0 comments

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