7 ms·

Compiling code into silicon

134 points by adapteva 5y ago

pezzana 5y ago
> ... Compiling simple programs into silicon should be like using llvm or gcc: fast, automated, and accessible. Some benchmarks would have been helpful. What kind of performance gain are there to make?
- jawnv6 5y ago
  The execution time is going to seem really zippy after the 8 week wait for the chips to be fabbed.
- nojs 5y ago
  I’d also like to know this. In general, what performance gains would one expect to see from an IC custom made for a very specific algorithm versus a modern CPU?
- artisanspam 5y ago
  This isn't a compiler. All this is is a build tool that calls compilers in the background. So benchmarks for this tool aren't really useful. However, for benchmarks between actual FOSS SystemVerilog compiler front-ends (i.e. language parsing), I've found this[1] chart from CHIPS Alliance to be useful. Some of the tools listed are parsing + synthesis (yosys) or front-end + simulator (icarus, verilator). Several are just parsers. [1]: https://chipsalliance.github.io/sv-tests-results/ https://chipsalliance.github.io/sv-tests-results/
ChrisMarshallNY 5y ago
Hmm… I thought that this was a treatment of the classic “silicon compiler”[0]. It basically is, with Python, as opposed to the usual; which is generally subtypes of C or C++. That said, this is definitely a great way to handle some types of product development. It’s just that, once it becomes hardware, different rules apply to pretty much everything else in the project. [0] https://en.m.wikipedia.org/wiki/Silicon_compiler https://en.m.wikipedia.org/wiki/Silicon_compiler
- czbond 5y ago
  > It’s just that, once it becomes hardware, different rules apply to pretty much everything else in the project. YES! As a mostly software person, I worked on a hardware project a few years back. It was like being kicked into the distant past. I had to think about code quality, updates, support MUCH more than I'd ever needed to consider it in the past. As the movie trailer says "IN a world...." where code is practically set in stone, and changes can be infrequent, and require hardware upgrade cycles.... yuck.
- opencl 5y ago
  As far as I can tell this project is not about compiling Python into hardware. It's a build tool for Verilog written in Python.
  - Symmetry 5y ago
    I hear Bluespec is almost like compiling Haskell into hardware but I've never worked with it myself.
extheat 5y ago
So the purpose of this is basically to design an ASIC in code? I’m skeptical about “extreme silicon specialization” being the “most viable” replacement to Moore’s law. Has that not already been the case since forever? The compute intensive things has already been moved onto specialized chips ala GPUs, TPUs, etc.
- ancharm 5y ago
  Think of this product as infrastructure-as-code for the Silicon/ASIC workflow. It's a pythonic API for the ASIC/VLSI workflow as opposed to the traditional spaghetti script TCL nightmare that holds together modern ASIC flows.
- whatsakandr 5y ago
  While I only really know what and FPGA is, I wonder if we're going to see a good amount of die area dedicated to an FPGA in the future, allowing software to define a new hardware accelerator for different tasks.
throwaway894345 5y ago
When I’ve inquired about this in the past I was told that relatively few programs compiled to silicon would outperform the same program running on a generalized chip (e.g., x86). Is this not the case?
- chriswarbo 5y ago
  It depends on your definition of performance. ASICs can have much lower power requirements (which is why they're used for mining Bitcoin)
- Symmetry 5y ago
  For a lot of algorithms like mining bitcoins or decoding a video directly in silicon you'll get a couple of orders of magnitude improvement in power efficiency. But these are fairly simple algorithms without any recursion, not much control flow divergence, and predictable memory access patterns.
- ldiracdelta 5y ago
  Not a chance. Dedicated sillicon hardware for a given domain is vastly faster -- normally an order of magnitude or more. The real question is do you have $10 million dollars for a sillicon mask set to fab your first chip?
  - throwaway894345 5y ago
    Does this factor in memory access and so on? Or is it scoped to tight numeric computing?
    - vlovich123 5y ago
      It's not scoped to anything. Think of it like assembly. If you understand your problem domain at a sufficiently deep level, you can design a more optimal architecture. For example, Google TPUs don't just have fast-paths for numeric computing. They change the memory layout & chip communication architecture to optimize for ML workloads so that your chip is constantly fed with data and not bottlenecked on memory access or cross-chip communication (in addition to direct dedicated access to a large memory that stores your data set which requires synchronization with system RAM and cross-chip cache invalidation, there's dedicated on-chip memory that's usable as scratch/storing a part of the data set that doesn't need any of that). There are of course potentially problems that aren't made meaningfully faster by going to ASIC just as there are problems where going from ASM to C++ or C++ to JS don't benefit. However, typically any problems that are hitting some kind of performance bottleneck could benefit & then it just becomes a matter of cost vs reward.
chriswarbo 5y ago
My favourite approach for this is "compiling to categories" http://conal.net/papers/compiling-to-categories http://conal.net/papers/compiling-to-categories Essentially: lambda calculus (and hence functional programming) can be given many different interpretations; whilst we usually interpret it as a computer program describing some result value, we can also interpret it as a circuit description, and turn it directly into hardware.
lloydatkinson 5y ago
I wonder why the homepage doesn't mention FPGA or ASIC once?
jimmyswimmy 5y ago
Pretty neat, a python tool that converts Verilog to an IC layout so that you can make your own custom SOC (assuming you have a substantial budget to pay for fab). Since it's not clearly stated on the front page, I had to go digging to figure out what processes it supports. Looks like FreePDK45, which is "an open-source generic process design kit (PDK) (i.e., does not correspond to any real process and cannot be fabricated)" [0], ASAP7 "Warning Work in progress (not ready for use)" [1] and Skywater130 which "As of May 2020, this repository is targeting the SKY130 process node. If the SKY130 process node release is successful then in the future more advanced technology nodes may become available." [2] The floorplanner supports their ZeroSOC [3] which I guess is based on TitanSOC [4] If this sounds negative, it's not, I just couldn't figure out what processes this was intended for without digging. ASAP7 is Arm and NCSU, and Skywater130 is Skywater and Google. [0] https://github.com/mflowgen/freepdk-45nm https://github.com/mflowgen/freepdk-45nm [1] https://docs.siliconcompiler.com/en/latest/reference_manual/pdks.html https://docs.siliconcompiler.com/en/latest/reference_manual/... [2] https://github.com/google/skywater-pdk https://github.com/google/skywater-pdk [3] https://github.com/siliconcompiler/zerosoc https://github.com/siliconcompiler/zerosoc [4] https://github.com/lowrisc/opentitan https://github.com/lowrisc/opentitan
- adapteva 5y ago
  Thanks for reading the docs! The only open manufacturable PDK is skywater 130, I wish there were more. Flow supports other commercial PDKs but for obvious reasons we can't publish those.
lou1306 5y ago
Personally I have fond memories of MyHDL [0], which may be seen as another "code-to-silicon" converter (or at least as the first step of a code-to-silicon workflow). I used it only briefly, and on a school project that had surprisingly little to do with actual hardware design [1], but it really felt "Pythonic" in the best possible way. [0]: https://www.myhdl.org/ https://www.myhdl.org/ [1]: https://github.com/lou1306/gssi/tree/master/2pc https://github.com/lou1306/gssi/tree/master/2pc
OneTimePetes 5y ago
Is this for ASICs or permanent SOC type solutions?
mediocregopher 5y ago
> Process scaling is coming to an end and it is a social imperative that we find a new path to extend the Moore's Law exponential. ... is it? Are our human rights at risk here? This sentence feels weird.
- ClumsyPilot 5y ago
  Indeed, I can think of a few areas of progress where social imperative is much greater, such as agriculture, healthcare and carbon free energy
  - mediocregopher 5y ago
    Can you explain _why_ it's so important to you? I literally don't get it, but I've also always assumed Moore's Law would run out eventually, so my worldview has that baked in.
  - hinkley 5y ago
    You can only solve the problems you understand, and human knowledge and civilization have expanded to the point where people are not interchangeable. I only know enough about the carbon and agriculture problems that I can explain them to other techies. I can't solve them. I can't even be sure my advice on which legislation needs to pass or be repealed is right. It's all a semi-educated guess. We are a giant parallel engine and insisting that we order all work crashes the capacity of the system to a rounding error. It's actively psychologically damaging because it gatekeeps people out of acknowledging that they can help be part of a solution instead of pretending to be silent witnesses to the effort of others.
    - ClumsyPilot 5y ago
      "insisting that we order all work crashes the capacity of the system to a rounding error" I am not arguing "no-one gets to party untill we solve world hunger", I am questioning the 'social imperative claim' - computer performance has improved what, 3-5x in the last 5 years? It's not clear to me how this has benefitted the average Joe in a measurable way, who is struggling to put food on the table. By contrast, if energy/food prices fell 5x, or became x more nutritious, the impact would be hard to miss. Even reduced prices of space rockets seem to have made more of a difference.
naikrovek 5y ago
why is this stuff almost always Python-based? Have we not learned? Python is a fine language, but it is dynamically type checked, and not compiled to binaries. There is so much evidence all around us that statically type-checked, compiled languages produce better, more performant code, and allow for application stability and longevity much more easily. I get that Python may be your favorite language, and that's fine, and that alone doesn't immediately qualify it as a good choice for anything, if you're being objective.
- maccam912 5y ago
  Agree that the best tool for the job should be used. In this case if python is gluing together different technologies to get this working it might have been the best tool for the job. Generally I would rather have my code compiled (into silicon in this case) be fast, even if it means the compiler itself is slower.
- jawnv6 5y ago
  This seems like a pretty egregious misreading of the project? Python isn't being lowered into silicon. It's a glue language for Boring Old Verilog that's been "compiled" into silicon since 1984. chip.set('source', 'heartbeat.v')
  - IshKebab 5y ago
    It seems you're right but I also misread it. I think it's badly written. Does this not sound like high level synthesis? > Process scaling is coming to an end and it is a social imperative that we find a new path to extend the Moore's Law exponential. The most viable option is extreme silicon specialization, which will require fast automated translation from program to silicon. Compiling simple programs into silicon should be like using llvm or gcc > development should be like programming in Python It actually seems like it is just a Python EDA build system. Python is still a terrible choice though.
    - jawnv6 5y ago
      I don't think the project is putting their best presentation forward, but the second image on the intro makes it pretty clear there's a .v/.sdc/.def file kicking around. Without any relevant tooling to develop, debug, or modify them, but it's clear the python is just shuffling deck chairs.
AshamedCaptain 5y ago
It's hard to say from the webpage, but this looks actually like a (frontend for a) place-and-route tool. No idea why to reinvent the terminology.
nobodywasishere 5y ago
This reminds me very much of edalize[1], which does something very similar. [1]: https://github.com/olofk/edalize https://github.com/olofk/edalize
etaioinshrdlu 5y ago
I'm having trouble understanding what this actually does. I think it wraps existing open source ASIC tools?
- krater23 5y ago
  Thats exactly my problem too.
ofou 5y ago
So much python here, but it gets the job done.
spullara 5y ago
Seems similar to the Chisel compiler for RISC-V: https://github.com/chipsalliance/chisel3 https://github.com/chipsalliance/chisel3
- logane 5y ago
  Chisel and this project are different; chisel is a programming language to design hardware while this is a build tool for hardware design. In software we have a nice compilation process that transforms code into machine code. However, to "compile" an ASIC you go from a hardware description language like verilog (which basically describes the design) and pass it through a complicated pipeline that composes a number of different tools. Right now, engineers use ad-hoc flows that use bash/TCL to glue together all the parts --- the project posted above is an attempt to cleanly specify + control the "compilation" process.
  - gsmi 5y ago
    I don't think it's either. I am pretty sure it is a competitor to OpenRoad. https://theopenroadproject.org https://theopenroadproject.org
    - adapteva 5y ago
      No, it it is not a competetitor to openroad. It's more like a build system, like how make sits on top of llvm. Openroad is one of the tools under the hood.
sydthrowaway 5y ago
How is this different to HLS
balaji1 5y ago
I was hoping, like others in this thread, to see something that takes HLL code and outputs a ASIC design. Of course it would have to be limited in the type of code it can take. It is similar to programming FPGAs. Are there applications that use FPGAs running close to CPUs in the cloud? Or CPUs are fast enough and much cheaper than using FPGAs.
m3kw9 5y ago
How is this different from FPGA?

134 points by adapteva 5y ago

> ... Compiling simple programs into silicon should be like using llvm or gcc: fast, automated, and accessible. Some benchmarks would have been helpful. What kind of performance gain are there to make?

jawnv6 5y ago
The execution time is going to seem really zippy after the 8 week wait for the chips to be fabbed.
nojs 5y ago
I’d also like to know this. In general, what performance gains would one expect to see from an IC custom made for a very specific algorithm versus a modern CPU?
artisanspam 5y ago
This isn't a compiler. All this is is a build tool that calls compilers in the background. So benchmarks for this tool aren't really useful. However, for benchmarks between actual FOSS SystemVerilog compiler front-ends (i.e. language parsing), I've found this[1] chart from CHIPS Alliance to be useful. Some of the tools listed are parsing + synthesis (yosys) or front-end + simulator (icarus, verilator). Several are just parsers. [1]: https://chipsalliance.github.io/sv-tests-results/ https://chipsalliance.github.io/sv-tests-results/

ChrisMarshallNY 5y ago

Hmm… I thought that this was a treatment of the classic “silicon compiler”[0]. It basically is, with Python, as opposed to the usual; which is generally subtypes of C or C++. That said, this is definitely a great way to handle some types of product development. It’s just that, once it becomes hardware, different rules apply to pretty much everything else in the project. [0] https://en.m.wikipedia.org/wiki/Silicon_compiler https://en.m.wikipedia.org/wiki/Silicon_compiler

czbond 5y ago
> It’s just that, once it becomes hardware, different rules apply to pretty much everything else in the project. YES! As a mostly software person, I worked on a hardware project a few years back. It was like being kicked into the distant past. I had to think about code quality, updates, support MUCH more than I'd ever needed to consider it in the past. As the movie trailer says "IN a world...." where code is practically set in stone, and changes can be infrequent, and require hardware upgrade cycles.... yuck.
opencl 5y ago
As far as I can tell this project is not about compiling Python into hardware. It's a build tool for Verilog written in Python.
- Symmetry 5y ago
  I hear Bluespec is almost like compiling Haskell into hardware but I've never worked with it myself.

extheat 5y ago

So the purpose of this is basically to design an ASIC in code? I’m skeptical about “extreme silicon specialization” being the “most viable” replacement to Moore’s law. Has that not already been the case since forever? The compute intensive things has already been moved onto specialized chips ala GPUs, TPUs, etc.

ancharm 5y ago
Think of this product as infrastructure-as-code for the Silicon/ASIC workflow. It's a pythonic API for the ASIC/VLSI workflow as opposed to the traditional spaghetti script TCL nightmare that holds together modern ASIC flows.
whatsakandr 5y ago
While I only really know what and FPGA is, I wonder if we're going to see a good amount of die area dedicated to an FPGA in the future, allowing software to define a new hardware accelerator for different tasks.

throwaway894345 5y ago

When I’ve inquired about this in the past I was told that relatively few programs compiled to silicon would outperform the same program running on a generalized chip (e.g., x86). Is this not the case?

chriswarbo 5y ago
It depends on your definition of performance. ASICs can have much lower power requirements (which is why they're used for mining Bitcoin)
Symmetry 5y ago
For a lot of algorithms like mining bitcoins or decoding a video directly in silicon you'll get a couple of orders of magnitude improvement in power efficiency. But these are fairly simple algorithms without any recursion, not much control flow divergence, and predictable memory access patterns.
ldiracdelta 5y ago
Not a chance. Dedicated sillicon hardware for a given domain is vastly faster -- normally an order of magnitude or more. The real question is do you have $10 million dollars for a sillicon mask set to fab your first chip?
- throwaway894345 5y ago
  Does this factor in memory access and so on? Or is it scoped to tight numeric computing?
  - vlovich123 5y ago
    It's not scoped to anything. Think of it like assembly. If you understand your problem domain at a sufficiently deep level, you can design a more optimal architecture. For example, Google TPUs don't just have fast-paths for numeric computing. They change the memory layout & chip communication architecture to optimize for ML workloads so that your chip is constantly fed with data and not bottlenecked on memory access or cross-chip communication (in addition to direct dedicated access to a large memory that stores your data set which requires synchronization with system RAM and cross-chip cache invalidation, there's dedicated on-chip memory that's usable as scratch/storing a part of the data set that doesn't need any of that). There are of course potentially problems that aren't made meaningfully faster by going to ASIC just as there are problems where going from ASM to C++ or C++ to JS don't benefit. However, typically any problems that are hitting some kind of performance bottleneck could benefit & then it just becomes a matter of cost vs reward.

chriswarbo 5y ago

My favourite approach for this is "compiling to categories" http://conal.net/papers/compiling-to-categories http://conal.net/papers/compiling-to-categories Essentially: lambda calculus (and hence functional programming) can be given many different interpretations; whilst we usually interpret it as a computer program describing some result value, we can also interpret it as a circuit description, and turn it directly into hardware.

lloydatkinson 5y ago

I wonder why the homepage doesn't mention FPGA or ASIC once?

jimmyswimmy 5y ago

Pretty neat, a python tool that converts Verilog to an IC layout so that you can make your own custom SOC (assuming you have a substantial budget to pay for fab). Since it's not clearly stated on the front page, I had to go digging to figure out what processes it supports. Looks like FreePDK45, which is "an open-source generic process design kit (PDK) (i.e., does not correspond to any real process and cannot be fabricated)" [0], ASAP7 "Warning Work in progress (not ready for use)" [1] and Skywater130 which "As of May 2020, this repository is targeting the SKY130 process node. If the SKY130 process node release is successful then in the future more advanced technology nodes may become available." [2] The floorplanner supports their ZeroSOC [3] which I guess is based on TitanSOC [4] If this sounds negative, it's not, I just couldn't figure out what processes this was intended for without digging. ASAP7 is Arm and NCSU, and Skywater130 is Skywater and Google. [0] https://github.com/mflowgen/freepdk-45nm https://github.com/mflowgen/freepdk-45nm [1] https://docs.siliconcompiler.com/en/latest/reference_manual/pdks.html https://docs.siliconcompiler.com/en/latest/reference_manual/... [2] https://github.com/google/skywater-pdk https://github.com/google/skywater-pdk [3] https://github.com/siliconcompiler/zerosoc https://github.com/siliconcompiler/zerosoc [4] https://github.com/lowrisc/opentitan https://github.com/lowrisc/opentitan

adapteva 5y ago
Thanks for reading the docs! The only open manufacturable PDK is skywater 130, I wish there were more. Flow supports other commercial PDKs but for obvious reasons we can't publish those.

lou1306 5y ago

Personally I have fond memories of MyHDL [0], which may be seen as another "code-to-silicon" converter (or at least as the first step of a code-to-silicon workflow). I used it only briefly, and on a school project that had surprisingly little to do with actual hardware design [1], but it really felt "Pythonic" in the best possible way. [0]: https://www.myhdl.org/ https://www.myhdl.org/ [1]: https://github.com/lou1306/gssi/tree/master/2pc https://github.com/lou1306/gssi/tree/master/2pc

OneTimePetes 5y ago

Is this for ASICs or permanent SOC type solutions?

mediocregopher 5y ago

> Process scaling is coming to an end and it is a social imperative that we find a new path to extend the Moore's Law exponential. ... is it? Are our human rights at risk here? This sentence feels weird.

ClumsyPilot 5y ago
Indeed, I can think of a few areas of progress where social imperative is much greater, such as agriculture, healthcare and carbon free energy
- mediocregopher 5y ago
  Can you explain _why_ it's so important to you? I literally don't get it, but I've also always assumed Moore's Law would run out eventually, so my worldview has that baked in.
- hinkley 5y ago
  You can only solve the problems you understand, and human knowledge and civilization have expanded to the point where people are not interchangeable. I only know enough about the carbon and agriculture problems that I can explain them to other techies. I can't solve them. I can't even be sure my advice on which legislation needs to pass or be repealed is right. It's all a semi-educated guess. We are a giant parallel engine and insisting that we order all work crashes the capacity of the system to a rounding error. It's actively psychologically damaging because it gatekeeps people out of acknowledging that they can help be part of a solution instead of pretending to be silent witnesses to the effort of others.
  - ClumsyPilot 5y ago
    "insisting that we order all work crashes the capacity of the system to a rounding error" I am not arguing "no-one gets to party untill we solve world hunger", I am questioning the 'social imperative claim' - computer performance has improved what, 3-5x in the last 5 years? It's not clear to me how this has benefitted the average Joe in a measurable way, who is struggling to put food on the table. By contrast, if energy/food prices fell 5x, or became x more nutritious, the impact would be hard to miss. Even reduced prices of space rockets seem to have made more of a difference.

naikrovek 5y ago

why is this stuff almost always Python-based? Have we not learned? Python is a fine language, but it is dynamically type checked, and not compiled to binaries. There is so much evidence all around us that statically type-checked, compiled languages produce better, more performant code, and allow for application stability and longevity much more easily. I get that Python may be your favorite language, and that's fine, and that alone doesn't immediately qualify it as a good choice for anything, if you're being objective.

maccam912 5y ago
Agree that the best tool for the job should be used. In this case if python is gluing together different technologies to get this working it might have been the best tool for the job. Generally I would rather have my code compiled (into silicon in this case) be fast, even if it means the compiler itself is slower.
jawnv6 5y ago
This seems like a pretty egregious misreading of the project? Python isn't being lowered into silicon. It's a glue language for Boring Old Verilog that's been "compiled" into silicon since 1984. chip.set('source', 'heartbeat.v')
- IshKebab 5y ago
  It seems you're right but I also misread it. I think it's badly written. Does this not sound like high level synthesis? > Process scaling is coming to an end and it is a social imperative that we find a new path to extend the Moore's Law exponential. The most viable option is extreme silicon specialization, which will require fast automated translation from program to silicon. Compiling simple programs into silicon should be like using llvm or gcc > development should be like programming in Python It actually seems like it is just a Python EDA build system. Python is still a terrible choice though.
  - jawnv6 5y ago
    I don't think the project is putting their best presentation forward, but the second image on the intro makes it pretty clear there's a .v/.sdc/.def file kicking around. Without any relevant tooling to develop, debug, or modify them, but it's clear the python is just shuffling deck chairs.

AshamedCaptain 5y ago

It's hard to say from the webpage, but this looks actually like a (frontend for a) place-and-route tool. No idea why to reinvent the terminology.

nobodywasishere 5y ago

This reminds me very much of edalize[1], which does something very similar. [1]: https://github.com/olofk/edalize https://github.com/olofk/edalize

etaioinshrdlu 5y ago

I'm having trouble understanding what this actually does. I think it wraps existing open source ASIC tools?

krater23 5y ago
Thats exactly my problem too.

ofou 5y ago

So much python here, but it gets the job done.

spullara 5y ago

Seems similar to the Chisel compiler for RISC-V: https://github.com/chipsalliance/chisel3 https://github.com/chipsalliance/chisel3

logane 5y ago
Chisel and this project are different; chisel is a programming language to design hardware while this is a build tool for hardware design. In software we have a nice compilation process that transforms code into machine code. However, to "compile" an ASIC you go from a hardware description language like verilog (which basically describes the design) and pass it through a complicated pipeline that composes a number of different tools. Right now, engineers use ad-hoc flows that use bash/TCL to glue together all the parts --- the project posted above is an attempt to cleanly specify + control the "compilation" process.
- gsmi 5y ago
  I don't think it's either. I am pretty sure it is a competitor to OpenRoad. https://theopenroadproject.org https://theopenroadproject.org
  - adapteva 5y ago
    No, it it is not a competetitor to openroad. It's more like a build system, like how make sits on top of llvm. Openroad is one of the tools under the hood.

sydthrowaway 5y ago

How is this different to HLS

balaji1 5y ago

I was hoping, like others in this thread, to see something that takes HLL code and outputs a ASIC design. Of course it would have to be limited in the type of code it can take. It is similar to programming FPGAs. Are there applications that use FPGAs running close to CPUs in the cloud? Or CPUs are fast enough and much cheaper than using FPGAs.

m3kw9 5y ago

How is this different from FPGA?