_quarks_

6 ms·

1.
A Transparent Wishbone-to-SPI Bridge Supporting Execute-in-Place (XIP)(github.com)
17 points by _quarks_ 5y ago|4 comments
2.
Show HN: A Tiny and Platform-Agnostic True Random Number Generator for Any FPGA(github.com)
5 points by _quarks_ 5y ago|1 comments
3.
by _quarks_ 5y ago
The neoTRNG provides a tiny (less than 70 LUTs) true random number generator for any FPGA. No device-specifc macros, libraries or attributes are used at all. The quality of the generated random numbers has been verified with the "dieha
4.
Show HN: A Technolgy-Agnostic Physical Unclonable Function (PUF) for Any FPGA(github.com)
1 points by _quarks_ 5y ago|1 comments
5.
by _quarks_ 5y ago
This is a tiny (less than 200 LUTs) Physical Unclonable Function hardware module for FPGAs. It provides a unique 96-bit "fingerprint" that can be used for security-related applications like key-generation or authentication. The fi
6.
A Dive into the Sipeed Tang FPGA(justanotherelectronicsblog.com)
22 points by _quarks_ 5y ago|1 comments
7.
Zephyr OS adds support for technology-agnostic soft-core RISC-V SoC(docs.zephyrproject.org)
4 points by _quarks_ 5y ago|0 comments
8.
by _quarks_ 5y ago
You cannot really maintain that. The controller has to adapt. That is what the two reset signals are for. The synchronous one can be trigger by application logic (for example some sort of timer) to re-calibrate the touch controller.
9.
A generic VHDL touch controller – add capacitive buttons to any FPGA(github.com)
77 points by _quarks_ 5y ago|17 comments
10.
Custom RISC-V Processor Built in VHDL(hackaday.com)
3 points by _quarks_ 5y ago|0 comments
11.
by _quarks_ 5y ago
The core provides (depending on configuration) ~0.9 coremarks per MHz. The base core has 32 GPIOs (32xinput + 32xoutput) and no DMA. If you need a DMA or more GPIOs you can attach them to the Wishbone/Axi interface.
12.
NEORV32: A customizable RISC-V SoC(blog.adafruit.com)
73 points by _quarks_ 5y ago|10 comments
13.
by _quarks_ 5y ago
I thought so, too. I have read about the Lattice MACH-NX having a secure enclave based on a RISC-V CPU, but it seems like this is just a soft-core CPU as well.
14.
by _quarks_ 5y ago
It is hard to compare two RISC-V cores if they do not have similar configuration options. For example: what kind of ISA extensions, supported traps, custom extensions, CSRs, etc. does VexRiscv "SmallAndProductive" configuration in
15.
Open-source soft-core RISC-V SoC with gdb support(github.com)
94 points by _quarks_ 5y ago|18 comments
16.
by _quarks_ 5y ago
Full-scale RISC-V soft-core microcontroller SoC with on-chip debugger compatible to openocd and GNU gdb
17.
Open-source RISC-V soft-core NEORV32 adds on-chip debugger support(github.com)
2 points by _quarks_ 5y ago|0 comments
18.
The NEORV32 RISC-V soft-core microcontroller(github.com)
1 points by _quarks_ 6y ago|1 comments
19.
by _quarks_ 6y ago
A size-optimized and highly customizable soft-core micorcontroller based on a rv32[i/e][m][a][c][b][Zfinx][Zicsr][Zifencei] +[u][PMP][HPM] CPU. The SoC includes internal memories/caches together with common peripherals like timer