3 ms·
A size-optimized and highly customizable soft-core micorcontroller based on a rv32[i/e][m][a][c][b][Zfinx][Zicsr][Zifencei] +[u][PMP][HPM] CPU. The SoC includ
by _quarks_ 6y ago
A size-optimized and highly customizable soft-core micorcontroller based on a rv32[i/e][m][a][c][b][Zfinx][Zicsr][Zifencei] +[u][PMP][HPM] CPU.
The SoC includes internal memories/caches together with common peripherals like timers, serial interfaces, Wishbone/AXI-connectivity, GPIO/PWM, a TRNG and even a dedicated Neopixel LED interface.
Written in platform-independent VHDL
Tested on Lattice, Intel and Xilinx FPGAs
Full-blown data sheet
Doxagen-based documentation of the software-framework (including FreeRTOS port)
BSD 3-clause license