3 ms·

NEORV32: A customizable RISC-V SoC

73 points by _quarks_ 5y ago

kken 5y ago
Why not link to the GitHub?` https://github.com/stnolting/neorv32 https://github.com/stnolting/neorv32 Also the Documentation https://stnolting.github.io/neorv32/ https://stnolting.github.io/neorv32/ This is absolutely one of the best documented free hardware projects that I have ever seen. Most company documentation is worse by far.
- UncleOxidant 5y ago
  Wow, that is good documentation. And it's VHDL too (which I prefer to Verilog).
  - wyager 5y ago
    IMO, VHDL and Verilog are both outstandingly terrible. There are tons of good options that compile from another language to VHDL/Verilog, such as Clash, Chisel, and nmigen. I cannot recommend strongly enough to use any of those over VHDL or Verilog. My personal favorite is Clash - it’s unusual in that it actually compiles the host language (a subset of Haskell) into VHDL/Verilog, rather than simply providing a library which you can use to create circuit objects. This means you can compile your hardware and run it like a normal program, or include it as a library, or whatever. Very nice for testing. You can also use arbitrary libraries as long as you don’t use anything that falls outside the compilable subset.
    - UncleOxidant 5y ago
      I'm kind of torn on the alternative HDLs. The HDL code they generate is often not very readable. When you're simulating you're effectively debugging that generated code. Generate statements in VHDL/System Verilog can often cover some of the use cases. Mostly I find them useful for testbench generation - that seems to be where things like Cocotb really shine.
      - tn1 5y ago
        For Chisel, the most popular tester Treadle has VCD dumps built in. That way you can do your behavioral debugging directly with the source. Of course, for anything involving timing etc you'll have to go with the relevant vendors' tools, which is typically Verilog/VHDL.
- api 5y ago
  It's not hard to do better than typical hardware vendor documentation.
ffhhj 5y ago
Where or when can we get these chips/boards?
- Narishma 5y ago
  The github readme lists at least 3 FPGA boards you can use.
varispeed 5y ago
I ran RV32 core on FPGA, it was useful but painfully slow. Does it really have only 32 GPIO? No DMA?
- _quarks_ 5y ago
  The core provides (depending on configuration) ~0.9 coremarks per MHz. The base core has 32 GPIOs (32xinput + 32xoutput) and no DMA. If you need a DMA or more GPIOs you can attach them to the Wishbone/Axi interface.

73 points by _quarks_ 5y ago

kken 5y ago

Why not link to the GitHub?` https://github.com/stnolting/neorv32 https://github.com/stnolting/neorv32 Also the Documentation https://stnolting.github.io/neorv32/ https://stnolting.github.io/neorv32/ This is absolutely one of the best documented free hardware projects that I have ever seen. Most company documentation is worse by far.

UncleOxidant 5y ago
Wow, that is good documentation. And it's VHDL too (which I prefer to Verilog).
- wyager 5y ago
  IMO, VHDL and Verilog are both outstandingly terrible. There are tons of good options that compile from another language to VHDL/Verilog, such as Clash, Chisel, and nmigen. I cannot recommend strongly enough to use any of those over VHDL or Verilog. My personal favorite is Clash - it’s unusual in that it actually compiles the host language (a subset of Haskell) into VHDL/Verilog, rather than simply providing a library which you can use to create circuit objects. This means you can compile your hardware and run it like a normal program, or include it as a library, or whatever. Very nice for testing. You can also use arbitrary libraries as long as you don’t use anything that falls outside the compilable subset.
  - UncleOxidant 5y ago
    I'm kind of torn on the alternative HDLs. The HDL code they generate is often not very readable. When you're simulating you're effectively debugging that generated code. Generate statements in VHDL/System Verilog can often cover some of the use cases. Mostly I find them useful for testbench generation - that seems to be where things like Cocotb really shine.
    - tn1 5y ago
      For Chisel, the most popular tester Treadle has VCD dumps built in. That way you can do your behavioral debugging directly with the source. Of course, for anything involving timing etc you'll have to go with the relevant vendors' tools, which is typically Verilog/VHDL.
api 5y ago
It's not hard to do better than typical hardware vendor documentation.

ffhhj 5y ago

Where or when can we get these chips/boards?

Narishma 5y ago
The github readme lists at least 3 FPGA boards you can use.

varispeed 5y ago

I ran RV32 core on FPGA, it was useful but painfully slow. Does it really have only 32 GPIO? No DMA?

_quarks_ 5y ago
The core provides (depending on configuration) ~0.9 coremarks per MHz. The base core has 32 GPIOs (32xinput + 32xoutput) and no DMA. If you need a DMA or more GPIOs you can attach them to the Wishbone/Axi interface.