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Chisel by definition can ONLY generate synthesizable Verilog.
by _chris_ 11y ago
Chisel by definition can ONLY generate synthesizable Verilog.
- rjsw 11y agoIt wasn't doing for rocket when I tried building it at the weekend and won't even build RISC-V at all right now. Feel free to fix it.
- gluggymug 11y agoThere's two possibilities. - Rocket has no automated build flow that checks whether committed code is synthesizable. - you aren't using the same flow as them. I struggled to find what synthesis tools they used just now so I don't blame you!
- rjsw 11y agoThe code that is committed isn't directly synthesizable, it needs to be transformed to HDL by a tool that is itself being updated. I tried what looked to be a supported flow, generate Verilog for FPGAs then synthesize it for Xilinx Zynq devices. The Verilog errors looked correct to me.
- gluggymug 11y agoI saw a little info on that at https://github.com/ucb-bar/fpga-zynq https://github.com/ucb-bar/fpga-zynq I guess you are referring to that? It's supposed to be a relatively mature tool so there's got to be a version that works ok.
- _chris_ 11y agoThen please submit an issue to the github issue queue. Don't complain on some internet forum and hope that somebody will read your mind. It works fine for me.
- rjsw 11y agoI don't have a github account. I just suggested a reason why someone might choose to use a conventional HDL.
- _chris_ 11y agoSure, I don't mean to suggest there aren't valid reasons for writing cores in VHDL, etc., I just want to clarify that Chisel (unlike say Verilog) will, by fiat, only ever generate synthesizable code. If that's ever not the case, you should let them know.