Sure, I don't mean to suggest there aren't valid reasons for writing cores in VHDL, etc., I just want to clarify that Chisel (unlike say Verilog) will, by fiat,

Sure, I don't mean to suggest there aren't valid reasons for writing cores in VHDL, etc., I just want to clarify that Chisel (unlike say Verilog) will, by fiat, only ever generate synthesizable code. If that's ever not the case, you should let them know.