TanjB

6 ms·

1.
by TanjB 2y ago
No, this is panels from which interposers will be made. Which are now larger than chips and rectangular, so wasted edges from a 300mm wafer are high. The proposed size is much larger than chip-grade ingots. They don't need perfect si
2.
by TanjB 3y ago
MIPS had load const to high or low half. More that 40 years ago Transputer had shift-and-load 8 bit constants. Lots of ancient precedents for rare big constants.
3.
by TanjB 3y ago
Interesting idea. Effectively moving the extra decode stage in front of the Icache, making the Icache a bit like a CISC trace/microOp cache. On a 512b line you would add 32 bits to mark the instruction boundaries. At which point you
4.
by TanjB 3y ago
When Moore wrote in 1965, commercial use of MOS was 10 years in the future and Dennard scaling would not become widely understood and stirring interest in CMOS until 15 years in the future. So, he was actually observing an era much like no
5.
by TanjB 3y ago
DRAM is not greatly affected by radiation, because the capacitors are large structures relative to radiation events. SRAM is affected, which is why SRAM arrays should always use SECDED ECC. The dominant cause of DRAM failures is bit flips
6.
by TanjB 4y ago
Those cell sizes are theoretical anyway. They do exist, but on sample chips optimized for SRAM. If you design a chip and select an IP macro for SRAM the density you actually get may be 3x or larger per bit. This is due to compromises on
7.
by TanjB 4y ago
Nice idea, but I honestly don't think it has much value for study. It was a solution to a problem which is no longer important, and what impressed David (and was fun for me) was implementing it under constraints (8086) that are no lon
8.
by TanjB 4y ago
TeX was beautiful. Both the algorithms (it was a masterwork on typesetting, still a good reference for anyone doing text layout) and the book.
9.
by TanjB 4y ago
Hi David, thanks for the kind words. I still have the source for that I think, it was written around 1984 originally for a project of my own, then sold to Logitech, Zorland, and Borland (before I went to work for Borland). The Borland one
10.
by TanjB 5y ago
Memory fail. No ECC, uses DDR4 instead of LPDDR4x (which has a 1-bit ECC and superior bandwidth) which the Tiger Lake CPUs would support.
11.
by TanjB 5y ago
Apple is probably paying closer to $20k per wafer, including test and packaging. There have been leaks on pricing in the industry, leading edge process is expensive. Even at 50M chips. TSMC is in a position to command a price that pays t
12.
by TanjB 5y ago
Ironic. CMP was developed and perfected at IBM, who used it to make complex low volume products. Excellent insight. CMP and damascene metal (guess who!) really kicked CMOS into top gear.
13.
by TanjB 7y ago
Some of the issues in the original paper are real (except the hologram where they have transformed marketing hype for stereo images into a real expectation of transmitting holograms). Pretty much all of them are capable of being implemente