RaisingSpear

9 ms·

31.
by RaisingSpear 3y ago
I can't see how it's any different. If you have 0x0y0z, a shift+or gives 0x0yxz, so the result is same as what you have, just with fewer operations.
32.
by RaisingSpear 3y ago
That's kinda neat. Actually, if you're doing that, you may as well reduce it to a single shift+or: a = ((a >> 12) | a) & 0xfff You could also skip the xor with 0x303030 by adjusting the lookup table accordingly. Unfortu
33.
by RaisingSpear 3y ago
My attempt to fix it: https://godbolt.org/z/P3e8q45qx (also removes the 64-bit multiply, which might be slow on 32-bit machines)
34.
by RaisingSpear 3y ago
Don't forget a middle-endian machine too!
35.
by RaisingSpear 3y ago
How are you packing the number into 12 bits? Multiple shift+and+or operations? If so, I'd expect that to generally be slower than a multiply+shift.
36.
by RaisingSpear 3y ago
No, it's like func("22", 2) If you're not familiar with C, you might be unaware that there needs to be some way for code to know where the end of the string is. Supplying the length is a common way to achieve this (this
37.
by RaisingSpear 3y ago
Ah that makes more sense. It's easy to get confused with RVV, given all the acronyms and config options. Despite it's "RISC" background, I find it much more complex and confusing than AVX and SVE.
38.
by RaisingSpear 3y ago
> I suppose large LMUL implementations would need to tag vector registers with their vl to make this work Again, I'm only considering LMUL=1 here. You'd need to also tag how tail elements are handled; tail undisturbed probably
39.
by RaisingSpear 3y ago
> It does for ara but not for all other implementations I could get my hands on (which all have a VLEN of 128 or 256, so relatively small). I generally would expect it to have no effect, because it's difficult to base scheduling&#x2
40.
by RaisingSpear 3y ago
Using LMUL > 1 likely kills vrgather performance, so I'd always use LMUL=1. VL doesn't affect the table AFAIK - it only affects what's written out. The table doesn't need to be more than 128 bits, but I don't th
41.
by RaisingSpear 3y ago
Interesting, a 4096-bit vector ISA. How well does it perform with widen/narrow and vrgather (IMO the most important instruction)?
42.
by RaisingSpear 3y ago
Keep in mind that many CPUs out there don't support those instructions (notably Intel's Skylake and ARM's Cortex A72). BLAKE3 will be significantly faster than SHA2 on many platforms out there.
43.
by RaisingSpear 3y ago
Not even close. CRC32 can easily run at >50GB/s single thread on this i7-12700K CPU (VPCLMULQDQ implementation). The BLAKE3 page claims around 7GB/s single thread. Fudging the figures a bit to cater to CPU differences, BLAKE
44.
by RaisingSpear 3y ago
It's counter-intuitive to think that way. Modern x86 is designed to primarily operate out of the uOp cache. You can argue about the cost of the uOp cache being expensive, but it's disingenuous to ignore it.
45.
by RaisingSpear 3y ago
Zen4 has an 8 wide frontend (from uOp cache) but 6 wide rename, making the overall design 6 wide. Decode is 4 wide, but that only matters for code not sourced from the uOp cache (which is quite large). Apple don't publish much details
46.
by RaisingSpear 3y ago
Modern x86 (Golden Cove, Zen 3/4) is currently 6 wide. [ https://i0.wp.com/chipsandcheese.com/wp-content/uploads/2021... ] A17/M3 is 9 wide [ https://files.catbox.moe/vkbop7.png ] From
47.
by RaisingSpear 3y ago
> At their scale maybe they're worried about collisions? With their scheme, collisions are already guaranteed to happen if they have >256 users.
48.
by RaisingSpear 3y ago
Your first link comes up as blank for me (documentation-service.arm.com returns 404 for me). But it's worth pointing out that X4, A720 and A520 support asymmetric MTE [1] - just the A720 page you linked to fails to mention it. [1] htt
49.
by RaisingSpear 3y ago
big.LITTLE allows a hybrid micro architecture, but all cores must support the same instruction set architecture. Even SVE must use the same vector width across all cores, which makes it unlikely that >128b SIMD will ever show up on cons
50.
by RaisingSpear 3y ago
> would you happen to know of any? I doubt I know any more than you. ARM's info on the matter is a little scarce, and I struggle to understand their documentation at times.
51.
by RaisingSpear 3y ago
This doesn't sound quite right - RVV has 100% fixed length vectors that can't vary in length. If setting VL is enough to qualify (which seems to be such a minor differentiating factor), then I'd argue that SVE also qualifies
52.
by RaisingSpear 3y ago
> SVE2 doesn't have a dynamic vector length like RVV SVE and RVV are no different in that regard. Note that RVV's VL doesn't alter the vector length - it's just an alternative way of masking (which can easily be impl
53.
by RaisingSpear 3y ago
To add on: SVE/RVV also have fixed size vectors. It's just that the size is specified by the hardware, whilst for AVX, software specifies the size.
54.
by RaisingSpear 3y ago
Both are true. Some Atom line processors were branded Pentium/Celeron. The low end big core SKUs were also branded Pentium/Celeron (and often had features disabled).
55.
by RaisingSpear 3y ago
> There is significant overhead involved Current CPUs already do this, and have been doing so for quite some time. And AVX10/128 doesn't alleviate it either.
56.
by RaisingSpear 3y ago
Interesting, I didn't know. It's the second link here: https://duckduckgo.com/?q=raspberry+pi+5
57.
by RaisingSpear 3y ago
> Leaked Isn't a lot of RPi5 info now public? For example: https://www.phoronix.com/review/raspberry-pi-5-benchmarks
58.
by RaisingSpear 3y ago
Are you sure? I just checked Intel's manual, and nothing above Sapphire Rapids is listed in AVX10.1: https://files.catbox.moe/23ty0y.png I couldn't find any new AVX* instructions added to Granite Rapids (I see PR
59.
by RaisingSpear 3y ago
AVX10.1 is just Sapphire Rapids' AVX-512 renamed, so arguably SPR (and early Alder Lake) already support AVX10.1, just without declaring the relevant CPUID bits. Client support depends on E-cores supporting it, and Intel have specified
60.
by RaisingSpear 3y ago
> Are the avx-10 instructions going into this generation? Nope. In fact, it probably won't be in client until after Lunar Lake (2025+).

More ›