> I suppose large LMUL implementations would need to tag vector registers with their vl to make this work Again, I'm only considering LMUL=1 here. You'd need

> I suppose large LMUL implementations would need to tag vector registers with their vl to make this work Again, I'm only considering LMUL=1 here. You'd need to also tag how tail elements are handled; tail undisturbed probably won't work, so it'd only work with tail agnostic, and if the processor always sets tail elements to -1. It'd also be more complicated with LMUL>1, since the processor would have to check the tagged VL for all registers in the group. And having scheduling depend on multiple register values is going to be problematic, but it's probably doable if high performance isn't a major concern. In general, it's wrong to think of VL meaning "vector length". It's more accurate to think of it as an additional mask such that mask=(1<<vl)-1