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big.LITTLE allows a hybrid microarchitecture, but all cores must support the same instruction set architecture. Even SVE must use the same vector width across
by RaisingSpear 3y ago
big.LITTLE allows a hybrid microarchitecture, but all cores must support the same instruction set architecture.
Even SVE must use the same vector width across all cores, which makes it unlikely that >128b SIMD will ever show up on consumer cores in the near future:
https://gist.github.com/zingaburga/805669eb891c820bd220418ee3f0d6bd#sve2---scaling-from-128-bit-to-128-bit https://gist.github.com/zingaburga/805669eb891c820bd220418ee...
- pjmlp 3y agoNo they don't, picking the first example "Armv9.2 - DynamIQ big.LITTLE - DynamIQ Shared Units-120" https://developer.arm.com/documentation/102484/0001/The-Cortex-X4--core/Supported-standards-and-specifications?lang=en https://developer.arm.com/documentation/102484/0001/The-Cort... https://developer.arm.com/Processors/Cortex-A720 https://developer.arm.com/Processors/Cortex-A720 https://developer.arm.com/Processors/Cortex-A520 https://developer.arm.com/Processors/Cortex-A520 You will notice that for e.g. Asymmetric MTE isn't supported across all of them, and the differences in microarchitecture are enough to have impact in the kind of instructions being used.
- RaisingSpear 3y agoYour first link comes up as blank for me (documentation-service.arm.com returns 404 for me). But it's worth pointing out that X4, A720 and A520 support asymmetric MTE [1] - just the A720 page you linked to fails to mention it. [1] https://www.arm.com/blogs/blueprint/memory-safety-arm-memory-tagging-extension#h-what-is-arm-s-latest-mte-development https://www.arm.com/blogs/blueprint/memory-safety-arm-memory...
- Symmetry 3y agoI'm not sure the parenthetical "including Asymmetric MTE" in one doesn't mean it isn't present in the other, especially since the lists are otherwise in different orders and just generally seem to be written by different persons.