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interesting to be reminded that an 8080 (8 bit datapath) took 4,800 transistors an Apple M5 Max is 100,000,000,000 transistors (ok it’s 18 CPU + 40 GPU cores)
by librasteve 1mo ago
interesting to be reminded that an 8080 (8 bit datapath) took 4,800 transistors
an Apple M5 Max is 100,000,000,000 transistors (ok it’s 18 CPU + 40 GPU cores) by comparison so 17 million 8080 equivalents
- TacticalCoder 1mo agoYup and Moore's law about transistors doubling every 18 to 24 months did basically hold, which is even more impressive. Foreseen it was.
- flohofwoe 1mo agoNitpicking, but since the M5 includes cache and GPU a more realistic comparision would probably be to count all transistors in an entire 8-bit home computer system against a modern integrated GCPU (e.g. from googling around a C64 might have around 0.75 million transistors, most in the memory chips). And in a way, those old 8-bit home computers also worked like a single integrated 'super-chip', because the whole system was driven by a single clock and entirely 'hard realtime', while modern computers are much more asynchronous (and I guess this asynchronous design is what enabled most performance improvements that go beyond pure transistor count scaling).
- dosisking 1mo agoThis is understandable, considering that the M5 is the Ultimate Computer, powered by Dr. Richard Daystrom's very own engrams
- librasteve 1mo agoexcellent point
- ThrowawayR2 1mo agoBut the M5 is clearly not safe to use in Enterprise¹ computing environments. ¹ USS Enterprise, that is.
- dofm 1mo agoThe ARM 1 only had 25,000 or so.
- librasteve 1mo agowonders how ARM did that - the MIPS R2000 came in at ~115k and the 80286 ~134k anyway - say you want 50% of the transistors for on chip RAM these days, then thats 100 billion / 50 thousand = 2 million ARM 1s clocking at say 3GHz 6e15 MIPS = 6 peta MIPS so if you could run code on it, you would get a 10,000x speed up ;-)
- tyingq 1mo agoA fairly deep dive into it https://www.righto.com/2015/12/reverse-engineering-arm1-ancestor-of.html https://www.righto.com/2015/12/reverse-engineering-arm1-ance...
- icelusxl 1mo agoARM1 has no cache memory, no hardware multiply and division, no MMU and no cache.
- dofm 1mo agoYeah — even ARM2 has no divide, as far as I recall from my days with an A310.
- librasteve 1mo agoWell even in deep pipelined FPUs (I'm thinking Weitek 1167 for example), the "divide" instruction is microcoded ... this chip had a full IEEE P764 64-bit single cycle barrel shifting MAC ... but divide was built via a special "3-bit and guess" kind of long division that was microcoded. MAYBE someone has built a hardcoded divider these days - but that would be a waste if good transistors in typical instruction mix.
- spacedcowboy 1mo ago> wonders how ARM did that Acorn co-founder Hermann Hauser famously joked that he gave the original ARM microchip design team two distinct advantages: no time and no resources. With no money for a large crew or complex hardware, the tiny core team had to keep the processor design exceptionally simple, which ultimately birthed the revolutionary RISC architecture. It also had to run in simulation on a BBC micro… Probably with a second processor via the Tube interface, but still.
- Someone 1mo ago> so 17 million 8080 equivalents At, ballpark, 1000 times the clock frequency. It’s a pity we do not how to connect such a large number of tiny cores in a way so that it can perform meaningful work. One hurdle is that, even ignoring the insane amount of connections needed, it would not be possible to connect each of those cores to each other one because their address spaces are so tiny.
- librasteve 1mo agoyeah, i have the notion that a grid would be good enough
- ErroneousBosh 1mo ago> It’s a pity we do not how to connect such a large number of tiny cores in a way so that it can perform meaningful work Every so often someone reinvents the transputer, and it turns out not to be quite as good as mainstream multi-core CPUs, but the wheel must turn.
- imtringued 1mo agoCerebras built the wafer scale engine so I'm not sure what you're pitying.