icelusxl

5 ms·

1.
by icelusxl 1mo ago
ARM1 has no cache memory, no hardware multiply and division, no MMU and no cache.
2.
by icelusxl 2mo ago
Compilers like GCC and Clang treat C's "long double" type by default as 80-bit wide and result in x87 generated code. This can be overridden to use either 64-bit or 128-bit floating point values.
3.
by icelusxl 4mo ago
Memory mapping/bank switching was fairly common on 8-bit and 16-bit systems, where a small memory window was used to select different memory banks, allowing a program to access more memory in chunks. Game consoles like NES, SNES and Ga
4.
by icelusxl 4mo ago
> There are only a handful of different instructions that account for 90% of all operations executed, and, near the top of that list are addition and subtraction. On ARM these can optionally set the four-bit NZCV register, whereas on x86
5.
by icelusxl 4mo ago
Yes, Turbo Pascal 5.0 introduced those features in 1988. https://www.youtube.com/watch?v=UNx4dxXptUg
6.
by icelusxl 6mo ago
Virtualize macOS 26 for testing purposes: https://eclecticlight.co/2025/01/21/what-can-you-do-with-vir...
7.
by icelusxl 6mo ago
It still is. The CPU's register renamer can detect these instructions to not have data dependencies and can zero the register itself. It doesn't send the instruction to the execution engine meaning they use no execution resources
8.
by icelusxl 6mo ago
The "Performance Improvements in .NET" blog lists the new JIT support for instruction sets each year. https://devblogs.microsoft.com/dotnet/performance-improvemen...
9.
by icelusxl 2y ago
Also supported in .NET 9 * https://devblogs.microsoft.com/dotnet/performance-improvemen... * https://github.com/dotnet/runtime/pull/91227
10.
by icelusxl 2y ago
Maybe http://0x80.pl -- this site features mainly SIMD/SWAR code.
11.
by icelusxl 3y ago
Seems to be reported by Apple and looks a lot like this security update: https://support.apple.com/en-us/HT213906
12.
by icelusxl 3y ago
> "rotate and mask" series of instructions Sounds a lot like the PowerPC's rlwinm instruction. The PowerPC 600 series, part 5: Rotates and shifts https://devblogs.microsoft.com/oldnewthing/20180810-00&
13.
by icelusxl 3y ago
"rep stosb" has been optimized since Ivy Bridge CPUs. > Beginning with processors based on Ivy Bridge microarchitecture, REP string operation using MOVSB and STOSB can provide both flexible and high-performance REP string opera
14.
by icelusxl 3y ago
* Visualization: https://www.officedaytime.com/simd512e/ * Book: https://link.springer.com/book/10.1007/978-1-4842-4063-2
15.
by icelusxl 5y ago
€49/month at Hetzner. https://www.hetzner.com/dedicated-rootserver/matrix-apple