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TSMC 2nm Process Disclosure – How Does It Measure Up?
- sylware 2y agoSo, Intel has its better "18A" process and we have no idea when they will start production at scale and where? Weird.
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- Mistletoe 2y agoThe whole thing is incredibly frustrating to read because no one is providing any sort of data or graphs that are beyond something you would see in a commercial. > In terms of the overreaching Power, Performance, and Area (PPA), the paper states that the process delivers a 30% power improvement or 15% performance gain and >1.15x density versus the previous 3nm node. Since I know the nm numbers are meaningless anymore, it’s kind of an insult to the math of 3 to 2 to call these sorts of minor improvements that.
- MathMonkeyMan 2y agoI think that this graph sums it up pretty precisely: <https://semiwiki.com/wp-content/uploads/2025/02/Figure-1.jpg https://semiwiki.com/wp-content/uploads/2025/02/Figure-1.jpg> You see, the bars go up and to the right as indicated by the arrow. The thing at the top right, which is under discussion, is more than fifteen times better than the thing on the bottom left. This is a huge achievement.
- taspeotis 2y agoI know you’re joking but that graph is spurious: > We took the graph image, pulled it into Excel and created an Excel graph overlaying it with the 28nm bar normalized to 1 and then entering values for the other bars until they matched the graph. If we then build a set of bars starting at 28nm = 1 scaled up based on the TSMC announced node to node power improvements we get a total improvement of less than 9x. Nodes from N28 to N10 match well but from N7 on the bars on the graph show more improvement per node than TSMC has announced. Just the N3 to N2 bars on the graph show a 55% improvements versus the announced 30% improvement. > … > It isn’t clear what may be driving this difference, but it is a big disconnect. This may be why the graph was removed from the final paper.
- Ragnarork 2y agoNot sure if if this is way overblown in my head but this society, domain, and economy don't take asymptotic progress for an ok answer, and always have the pressure to deliver ever increasing performances and results, even when the law of physics become harder and harder to bend or circumvent. It shouldn't limit innovation and trying to go past those limits one way or another, but at some point it feels like marginal (or below expectations) progress isn't acceptable at least for a while. That it then has to become coated in some marketing lie or half-truths to mask reality and oversell what it truly is... That's still progress! And it can slow down, accelerate, who knows? This should be acceptable.
- high_na_euv 2y agoWhat do you mean? Intel says that 18A will be a thing around mid of 2025, so 4-6 months from now, I think. Then it will upgrade to HVM between Q3 and Q1 iirc
- ant6n 2y agoHVM?
- homebrewer 2y agoApparently, it's "high-volume manufacturing".
- sylware 2y agoWhere? And the scale is to supply the whole world?
- DebtDeflation 2y agoIn late 2013 Intel said 10nm was coming in 2015.
- adrian_b 2y agoThe first Intel product on 18A is the "Panther Lake" CPU for laptops. According to what Intel claims, it will be launched in H2 2025, i.e. with commercial availability either in October or in December, depending on how quickly Intel will succeed to improve the yields of the 18A process.
- m00dy 2y agofor those who are in the industry, it's just a marketing term.
- curiousObject 2y agoIt’s marketing, but everyone is doing it. So you have got to live with it. It’s exaggerated, but it still represents some degree of progress.
- wongarsu 2y agoA marketing term that will have to change. For the last couple decades every new, denser process generation just took the previous number and divided it by sqrt(2). That doesn't really work beyond 2nm. Intel invented a new number they can count down. Do we already know what naming scheme TSMC will adopt for the next generations?
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- hcfman 2y agoSuper interesting. Now what we really need is for Raspberry Pi to make a 2nm version so that the power usage becomes more acceptable for Wildlife and biodiversity use cases. Please, please Raspberry Pi, also make a 2nm version Actually, I think it's broadcom I need to ask that from isn't it ? (Although then I think it would almost become a Jetson) Please please NVidia make a 1nm Jetson, the planet needs you to.
- magicalhippo 2y agoThe current Pi 5 is on a 16nm node[1], down from 28nm for the Pi 4. So, far off needing a bleeding edge node[2] to see further improvements. [1]: https://chipwise.tech/our-portfolio/raspberry-pi-5/ https://chipwise.tech/our-portfolio/raspberry-pi-5/ [2]: https://www.tsmc.com/english/dedicatedFoundry/technology/logic https://www.tsmc.com/english/dedicatedFoundry/technology/log...
- hcfman 2y agoThe Pi is great! Just saying, running a Pi with an object detector on batteries draws around 9W. That's big batteries and solar or wildlife use cases. But think how cool it would be if it could run on 2W. Having said that. The Jetson runs at around 7W doing that and a lot faster inference. Just a lot more expense. Likely the Jetson will eventually be something like 2nm. So maybe we see around 4W at that time running an object detector. And of course the Jetson has the memory and processor together on it's modules so everything can benefit. Just dropping the power on the Pi for the processor leaves that out. But thanks for the links
- magicalhippo 2y agoJetson Nano was manufactured using the 20nm node as far as I can see[1]. Just goes to show manufacturing node isn't everything. There's a lot of various optimizations one can do depending on targets. Guess we'll just have to see what the future brings. [1]: https://en.wikipedia.org/wiki/Tegra#Tegra_X1 https://en.wikipedia.org/wiki/Tegra#Tegra_X1
- thiago_fm 2y agoIs there an advantage on going 2nm given the costs? Maybe somebody can clearly answer this here on HN, I love this subject! It's interesting how the whole valuation of TSMC(and some from NVidia) are aligned by their current advantage on the 3nm process. Intel on 18A is literally TSMC's 3nm process + backside power delivery, which means more power efficiency, performance also less heat. It's definitely what they need to get them back into the processor game and beat everybody, maybe we will see Apple doing designs with the Intel factory before 2030? Hope they don't fail their deadlines: summer this year to be producing 18A, and 2026 mass production.
- dannyw 2y agoFor datacenters and especially hyperscalers, the power and cooling bill is a huge part of the TCO. You make somewhat more power efficient chips, you get to sell it for a lot more. Your chips are inefficient, and you won’t be able to sell to a hyperscaler even for $0. The latter is the position Intel is quickly arriving at for DC; Epycs are much more efficient and Intel’s wildly slashing prices. — For Apple, A-series dies are pretty small, they basically prefund a large part of TSMC and almost certainly gets the lowest prices of any customer. That said, Apple’s strict fascination with always jumping to the latest node, even when it seems premature, puzzles me from the outside.
- Aperocky 2y ago> That said, Apple’s strict fascination with always jumping to the latest node, even when it seems premature, puzzles me from the outside. As a user of M1, M2 and M4, that's why I've chose Apple. I would have gladly jumped to any laptop that supports Linux with similar power and battery life and weight/build, unfortunately that computer does not exist. Is it time to call on garmin to make a computer? They've beat apple on the watch. I have faith in them.
- thunderbird120 2y ago>Intel on 18A is literally TSMC's 3nm process + backside power delivery, which means more power efficiency, performance also less heat. That's a pretty serious abuse of the word "literally" given that they have nothing in common except vague density figures which don't mean that much at this point. Here's a line literally from the article >Based on this analysis it is our belief that Intel 18A has the highest performance for a 2nm class process with TSMC in second place and Samsung in third place. Given what we currently know about 18A, Intel's process appears to be less dense but with a higher emphasis on performance, which is in line with recent Intel history. Just looking at the density of a process won't tell you everything about it. If density were everything then Intel's 14nm++++ chips wouldn't have managed to remain competitive in raw performance for so many years against significantly denser processes. Chip makers have a bunch of parameters they have to balance when designing new nodes. This has only gotten more important as node shrinks have become more difficult. TSMC has always leaned more towards power efficiency, largely because their rise to dominance was driven by mobile focused chips. Intel's processes have always prioritized performance more as more of their products are plugged into the wall. Ideally, you want both but R&D resources are not unlimited.
- ramshanker 2y agoHow much would the Non-Recurrent Cost associated with designing a RISC-V CPU using this 2nm? EDA Tools, Photo-Masks, One Time Chip Design Engineer Cost, Simulation/Virtual Verification and so on. I mean every thing till tape-out.
- selectodude 2y ago3nm was over a half billion. So if costs are going up at the same rate, over a billion dollars. https://semianalysis.com/2022/07/24/the-dark-side-of-the-semiconductor/ https://semianalysis.com/2022/07/24/the-dark-side-of-the-sem...
- monocasa 2y agoThat article refers to those charts by McKinsey as "incorrect" and instead gives a figure of $50M-$75M for 3nm.
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- adgjlsfhk1 2y agoRiscv doesn't need smaller nm. It just needs someone to actually design and release a good core design. 14nm (or 4 or anything in between) is perfectly suffient to make a Riscv chip 10x faster than any Riscv that currently exist.
- zozbot234 2y ago14nm or so is kind of a sweet spot for general purpose chip design right now, because later nodes turn out to have higher overall per-transistor cost despite the improvement in density and area. Of course this may well change over time as even finer production nodes get developed and the existing nodes then move closer to the trailing edge.
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- ajross 2y ago> This paper continued TSMC’s trend over the last several years of presenting marketing papers at IEDM instead of technical papers. [...] there are no pitches in the paper, no SRAM cell size, and that graphs are all relative Sigh. So basically we assume this is all aspirational spin and that either they haven't finalized the parameters for the process yet or they know the numbers will be disappointing already. The era of VLSI scaling is over for sure. Hilarious that Intel's complete failure at process development happened at exactly the moment where it could do the least damage.
- zozbot234 2y agoThat's not what they're saying - they say it's been a trend over the past several years. VLSI scaling is still continuing, and the article mentions that TSMC seems to have the best numbers, though at higher per-die cost than the authors expected or found reasonable.
- ajross 2y agoRight, that's the spin. You have to put a "seems to" on "have the best numbers" because there are no numbers. If there numbers were the "best", then they would give them. They did not. So... they probably aren't. Or there are other complexities they don't want to reveal.
- zozbot234 2y ago> If there numbers were the "best", then they would give them. They did not. So... they probably aren't. I'm not sure that we can say that. They may be keeping their cards close to their chest for any number of reasons. Unless they think they also had "bad" numbers in the past several years when they were doing the same thing.
- WhitneyLand 2y agoNo, that’s not how it works. TSMC publishes industrial research, not pure science research like a university. In this context the amount of detail they release is careful balance of PR benefit vs. competitive advantage vs. patent status vs. keeping their talent happy because good researches want their names in prestigious journals.
- Red_Comet_88 2y agoDoes anyone know why Nvidia chose to re-use the 4N process for their Blackwell series? From everything I've read, 3N is mature and is already in full production, yet Nvidia chose to just reuse 4N. It seems very much unlike Nvidia to leave performance on the table.
- newfocogi 2y agoMy guess is it's related to yield and/or large die sizes making them more susceptible to defects. I expect architectural changes in the Blackwell series matter more than performance improvements from process node.
- Strom 2y agoThe answer is probably profit margin. It's also not unusual at all for Nvidia to leave performance on the table in terms of production nodes. I mean just look at the RTX 3000 series which was made with Samsung 8LPH, categorized as a "10nm node". Even at the time, for a late 2020 launch, TSMC already had several generations which were better, in both the "7nm" an "5nm" categories.
- ksec 2y agoN3 is mature and is already in full production for small Mobile SoC only. The Blackwell goes up to ~750mm2 it is a completely different beast. And Nvidia is already having trouble trying to fill up their Blackwell on a higher capacity, relatively mature N4 Node. Imagine doing it on an expensive N3, and then charge $4999 only to get outrage as rip off on HN and reddit. Generally speaking the larger die size, high performance chip tends to be a node behind simply because all the leading edge node and tools aren't even designed for them but are specifically aiming at Mobile SoC. Then you add in cost issue and yield.
- adrian_b 2y agoN3B is used by Intel for its Lunar Lake, Arrow Lake S and Arrow Lake H CPUs and GPUs, so it is also in full production for high-power non-small and non-mobile chips. Of course, even if N3B is fine for desktop CPUs and for smaller GPUs, it may still have too low yields for chips of the size of the top models of NVIDIA GPUs.
- loandbehold 2y agoWhy are American fabs built in Arizona? What's so special about AZ?
- josaka 2y agoI suspect it's, in part, because humidity is low. The fab needs to tightly control humidity and temperature. Pulling water from air is energy intensive. Facilities team in the fab I used to work in said their most energy intensive days where the most humid days.
- bigtimesink 2y agoHumidity in Taiwan can be very high.
- mort96 2y agoAnd I'm betting that combatting that humidity is a significant cost for TSMC.
- sct202 2y agoMotorola put a bunch of their early semiconductor facilities there in the 1950s so there has been a long history of the industry there along with relevant suppliers and trained work force. Microchip Technology, Amkor, Intel, First Solar continued the trend in the 70s/80s so there's a lot of related industry built up over the decades.
- muricula 2y agoTax breaks and politics. https://www.nytimes.com/2023/02/22/technology/arizona-chips-act-semiconductor.html https://www.nytimes.com/2023/02/22/technology/arizona-chips-...
- UberFly 2y agoMain reasons are a stable geology and climate, access to reliable water via the salt river project that was designated for industrial use, and the historical semiconductor presence that is already in the area. The local universities also have a strong focus on tech.