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Ask HN: What does RISC-V custom chips for under $100K mean?
In 2016, SiFive blogged about custom chips for under $100K[1]. What does this mean in practice for a business? What does a business get if they give SiFive $100K? Does the business have to give SiFive anything in addition to $100K such as a schematic? What are the steps between giving SiFive $100K and getting physical chips in your hands?
> At the workshop, people asked me what it would cost to make a chip with SiFive. The room went quiet … people expected me to dance around the topic (like all other people do). Jaws dropped when I simply said “system architects and designers can get customized chips for less than $100,000” – less than the cost of just licensing most CPUs today.
[1] https://www.sifive.com/blog/custom-chips-for-under-100k
- brucehoult 2y agoIn 2016 that would be a E31 core, user-specified amount of data SRAM and icache (also SRAM), XIP from external SPI flash, user-specified number of GPIOs. Possibly integrating some simple customer peripheral IP as a memory-mapped device, or MAYBE with a simple custom instruction as a functional unit, SiFive doing a little NRE on that, and doing a $30k 180nm shuttle run giving ~300 chips. If you could give SiFive your desired peripheral or custom instruction already integrated with Rocket and working on an FPGA (Arty) then you'd get it for under $100k for sure -- if you made SiFive do the work it would rapidly get to be more. Disclaimer: I was an early customer for the HiFive1 (December 2016) and then worked at SiFive from early 2018 to early 2020, but I don't speak for them.
- zkirill 2y agoThanks for replying! This is one of those moments when one is reminded how amazing HN can be. So, for example, if a business sends SiFive $100K and a copy of OpenRISC, they would receive ~300 chips that could then be used in a commercial product? If a business then wants to order another 300 chips (or more), would they only need to pay SiFive the $30K? Does the $30K price fluctuate? Does E31 core have an end of life? In the event that EOL is reached, or SiFive ceases to exist, can the business make these chips somewhere else or are they screwed?
- brucehoult 2y agoI suspect SiFive wouldn't be too interesting in doing that. First off, OR1K is a lot bigger than an E31. And it's only a core, not an SoC. You're probably looking at a several million dollar job for that. Plus SiFive divested their chipmaking division, OpenFive (formerly Open-Silicon) in 2022. That would be who you'd want to talk to.
- vessenes 2y agoQuick note - I’ve been where you are on hardware, which I imagine is “interested and curious and might have a use case”. Silicon is an industry that is related to software, but in no way the same, and it’s a fairly complex stack, with its own unique supply chains and considerations. All that said, if you’re exploring, have fun! If you’re getting serious I’d recommend you find someone who can help you navigate it; there are many surprising things to learn as you go. For instance, to answer your question on chips: all chips are made by ‘taping out’ - a process that yields the masks that can be used to make chips. These are only good with a specific chip maker, and will live with that chip maker near the hardware that is used to make the chips forever. It’s expensive to design the chip, and expensive to tape out, but once you have something it’s relatively cheap to make more of them. 180nm is potato quality - many many generations behind. So far behind it might actually be more expensive to get chips than at 110/65nm, although I’m only speculating here. A shuttle run means the vendor is going to put your chip designs onto a wafer with a bunch of other ones at the same time; it’s a way to share out the costs for a tape out with other customers. The general idea of a 180nm tape out is likely that you want some parts to test in your infrastructure / build ahead of your full launch. Think of it like a compile with -debug turned all the way up. Usually you’d then either adjust the design and re-do a shuttle run (your compile turned up real problems or your use case changed), or you’d shrink and make your own wafer, (turn on optimization and compile for deployment). Shrinking from 180 to 110 or 65 is likely almost totally an automatic process these days; as you go smaller, analog physics makes this challenging. So, upshot: you probably could ask for another shuttle run, but you’d have a higher part cost than your first run because you’d be paying for the whole wafer alone this time, but only able to use the part that has your chips on it. And, you’d need to be in a world where you really wanted another 300 chips of the same potato speed (and possibly quality) as your first run. Most likely a silicon consultant would find a more efficient use case for your needs, whether that’s a small geometry FPGA that is programmable, an existing chip (there are A LOT of chips in the world), or some other solution. Anyway, have fun if you get into it — fascinating world.
- NonEUCitizen 2y agoHow were the 180nm chips packaged? Thanks.
- JonChesterfield 2y agoOptimistically tagging on here as it's a similar sort of question. Say one lone developer gets a bit carried away with verilog and ends up with a description for a chip. I know there's an odd lot style of thing where you can get your chip drawn on a wafer along with a load of other chips from other people. There's probably a way of getting someone who knows what they're doing to attach wires to it, wrap it in plastic or whatever else is involved in "packaging". Where does one get started with that, and what's the ballpark cost? I'm assuming a fair amount of the OP's $100k is SiFive labour, but I don't know how to guess whether a half dozen custom chips in some sort of packaging is of the order of 10s of dollars or 10s of thousands. (edit: I've done a lot of software near hardware and have a vague idea that uploading the data to tsmc was called "tape out" and involved quite a lot of money, but I also vaguely remember talking to someone at a conference who had chips made as a hobby so there are some pieces missing from my mental model)
- dfgs234 2y agoIf you just want to put your verilog into an ASIC then it can be done fairly inexpensively these days. For example: https://efabless.com/chipignite https://efabless.com/chipignite $10K for 100 packaged dies in QFN. Which is not totally out of hobby range (I've seen people spend way more on fixing up cars that have no business being fixed) and if you use their harness they'll solve most of the hard EE problems for you. But you might consider why you're making the IC. If it's for the experience, sure. But if it's to make a commercial product, there's a lot more to it. For example, what's your IO solution...
- JonChesterfield 2y agoNice example, thank you. I have no interest in making a commercial product but some motivation to learn what lies below the ISA. Like you say, that's cheaper than some more common hobbies. I work in the software side of semiconductor companies so it's a reasonable spin on professional development too. A friend recently discovered that PCBs can be ordered online for essentially zero cost and arrive in the mail and that surface mount soldering is an easy thing. Combined with a path for code to magic sand that's a whole world of dubious past times suddenly available.
- jpm_sd 2y agoI took a look at your blog[0]. You aren't going to need a custom CPU. You'll be much better off with something that's already in production, in the market, well-documented and well-tested. Also it sounds like you have a pretty steep learning curve ahead of you. [0] https://flyingcarcomputer.com/posts/a-new-personal-computer/ https://flyingcarcomputer.com/posts/a-new-personal-computer/
- corytheboyd 2y agoI’d love an actual description of how this will change personal computing. The blog post is just a bunch of small technical decisions and opinions, doesn’t mention anything about personal computing. Maybe they should build an OS variant instead? The home page blurb of “No AI. No cloud. No distractions” is already very attainable without inventing a new type of computer… Regardless, respect. Seems daunting, but will no doubt be a really cool project.
- svnt 2y agoThis is one of the kindest comments I have seen here.
- sircastor 2y agoIt's worth noting that if you're interested in making your own custom silicon, you can get it done quite inexpensively. It's not a fast process, but if you want to try your hand at building something that is all you, you can! This isn't want SiFive was doing - they're providing engineering expertise. Here you're allowed to put together all your own logic gates into... a thing. https://tinytapeout.com/ https://tinytapeout.com/
- brucehoult 2y agoTinyTapeout is cool, but the size of what you can do there is many orders of magnitude smaller than a Linux-capable OR1K core and surrounding SoC! The typical project is more like a binary counter, or a BCD to 7-segment decoder. I don't think you would even be able to fit a 6502 -- not the core, but also you can't have that many pins. I think one was done with a bit-serial SeRV RV32I CPU (which is 125 LUT6 and 164 flip-flops when done in a Xilinx FPGA), but without the CPU registers fitting on the chip.
- jononor 2y agoYeah it really is for tiny chips. It is fabulous learning experience though, which is also the purpose of the project. Maybe in a few years we will have Smalltapeout where we can do microcontroller/microprocessor grade in the same way.
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