dfgs234

3 ms·

1. 1.▲
   by dfgs234 2y ago

   I suppose it depends what they're printing and why. There are plenty of structures that will want to be 180nm and larger for many years to come. But I definitely agree that pretty soon it will make no sense to artificially limit print
2. 2.▲
   by dfgs234 2y ago

   You might find this course helpful then. There is a huge amount of information you need to consume to make an IC so having it all organized for you is pretty valuable. It will save you many, many, hours. :) https://zerotoasicc
3. 3.▲
   by dfgs234 2y ago

   That doesn't really match my experience. I could be totally wrong though because I don't get to look at the books. ASML it still announcing DUV systems on their product page. I would think this would mean they would be very happ
4. 4.▲
   by dfgs234 2y ago

   > The secret is that 180nm nodes are so legacy That's true but they keep upping the capabilities of what the designer can do at 180nm. Based on the wait times for my jobs, there's not a lot of spare cycles, at least at the fou
5. 5.▲
   by dfgs234 2y ago

   > 180 nm fabs are getting to the point where replacing machines is prohibitively expensive and spare parts have to be custom made. Do you have a reference for that? I'm not sure why it would be true. 180nm lines have many other adv
6. 6.▲
   by dfgs234 2y ago

   If you just want to put your verilog into an ASIC then it can be done fairly inexpensively these days. For example: https://efabless.com/chipignite $10K for 100 packaged dies in QFN. Which is not totally out of hobby rang