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Instruction Sets Should Be Free: The Case for RISC-V [pdf] (2014)
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- demondemidi 2y agoNo one said they shouldn't be. I mean, its not like there are laws saying they cannot be free. Patternson has always used too much hyperbole and marketing himself as a crusader. RISC-V is great, let the technology speak for itself.
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- DarkNova6 2y agoWith market forces being the way they are, the quality of technology is becoming increasingly irrelevant. What counts is having a dominant position so you can shove down your "product" right through everybody's throat.
- zarathustreal 2y agoWell not only that but choices about these kinds of things are often made by people that don’t necessarily know what options they have. Marketing is a big part of what choices people make because they don’t know what they don’t know
- baq 2y agoproduct? that's so 2010s. it's all about subscriptions now. you own nothing but please keep paying that sweet monthly/yearly fee.
- DarkNova6 2y agoI wanted to refrain from profanity and used “product” instead of “shit” ;-)
- demondemidi 2y agoReally? Wow, Western Digital and nVidia sure are having ARM rammed down their throat... oh wait, they are using RISC V. What are you even talking about?
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- CalChris 2y agoThere is also a response from ARM, The Case for Licensed Instruction Sets. https://web.archive.org/web/20140926222155/http://www.linleygroup.com/mpr/article.php?id=11268 https://web.archive.org/web/20140926222155/http://www.linley...
- snvzz 2y agoIt is appalling how stupid whoever at ARM must have been, to respond and thus bring attention to RISC-V. Back then, RISC-V was not anywhere as well-known as it is today.
- pavlov 2y agoSort of like when Ballmer-era Microsoft declared war on Linux and GPL.
- gregw2 2y agoStupid?! The type of reader paying $500/year for the Microprocessor Report (where this response article appeared) already knew. (Similarly if they were motivated to get it free or took time to read it through their university, company, pirate it, etc.) And the ARM response you'll didn't mention RISC-V by name specifically. The notion of an open source entity building an open or semi-open ecosystem cannibalizing even a low-end player was already happening in phone operating systems (Android/Linux vs Windows); a parallel dynamic wasn't lost on anyone looking at the hardware/ISA side, phone or non-phone. I don't see this as any more foolish than Bill Gates making the case for software licensing vs free software at the dawn of the PC revolution. You may disagree with one party or the other, but each laying out their case is a marketing must. If you want to compete at the low end, you have to explain your value proposition vs "free".
- pjmlp 2y agoAnd 40 years later, after FOSS folks thought to have won, everyone is going with open core, finally realising why businesses don't want anything to do with GPL like licensing. So anyone that thinks RISC-V isn't going to trail a similar path, is fooling themselves.
- fidotron 2y agoThere was a reimplementation of SuperH as https://j-core.org https://j-core.org some years ago and AFAIK it didn't really go anywhere, sadly. One of the things you get when dealing with OEMs, and IP licensors like Arm, is a huge amount of paperwork about patents, and I used to believe this was annoying, but have come to believe it is vital. The alternative "open" "free" approach leads to something like the cloud world, where in practice it's AWS/GCS/Azure and some others in lower tiers, because of the complexities around the open/free stacks and IP tarpits that result. Just look at how AWS behave. We must be able to pay to develop and license these pieces, or you will end up with all IP being trade secrets and the vertical monopolies will get utterly entrenched. There are definitely patent trolls around but the free case would be much stronger if financially viable open source software development were a thing.
- bee_rider 2y agoAmazon also, of course, designs ARM cores. But they do seem a tad less “locked in via complexity” than their cloud stuff. I wonder if that is a result of the license situation. Alternatively, Amazon may just not be very good at coming up with hardware extensions, and also trying to commoditize their complement.
- lizknope 2y agoAmazon does not design ARM cores. Graviton uses Neoverse cores licensed from ARM https://en.wikipedia.org/wiki/AWS_Graviton https://en.wikipedia.org/wiki/AWS_Graviton
- crote 2y agoSo rather than getting stuck in potential future tarpit of AWS or GCS or Azure, or probably a dozen other companies, we should voluntarily put ourselves into the IP tarpit developed by ARM? How exactly is that a win? Over the last two decades ARM has developed a stranglehold on the non-x86 world, and they have already considered abusing this position to increase their profit margin[0]. As a chipmaker you're essentially stuck with ARM, as getting rid of them means you not only need to redesign your chips, but you also need to completely overhaul the entire downstream ecosystem. With RISC-V there's at least the possibility of switching to a different IP vendor. That might not practically happen with bleeding-edge SoCs, but that kind of flexibility is quite important for the far larger dime-a-dozen MCU market. It's exactly why companies like Western Digital are investing in RISC-V and even developing open-source implementations[1]. Compute is essentially a commodity already, so why not tear down the walled gardens and force it to be one? [0]: https://www.techpowerup.com/300385/arm-could-change-licensing-model-to-charge-oems-directly https://www.techpowerup.com/300385/arm-could-change-licensin... [1]: https://blog.westerndigital.com/risc-v-swerv-core-open-source/ https://blog.westerndigital.com/risc-v-swerv-core-open-sourc...
- Koshkin 2y agoThe title of the piece is somewhat misleading - the actual point was, "there is no good technical reason for the lack of free, open ISAs."
- wtetzner 2y agoI wonder why this hasn't been an issue for Apple (or maybe it has?).
- zik 2y agoThey licensed the ARM ISA from ARM.
- 1000100_1000101 2y agoApple was a co-founder of Arm [0]. "Arm was officially founded as a company in November 1990 as Advanced RISC Machines Ltd, which was a joint venture between Acorn Computers, Apple Computer (now Apple Inc.), and VLSI Technology (now NXP Semiconductors N.V)." I'm not sure of their exact licensing terms, but I'm sure as a co-founder they're favourable. [0] - https://newsroom.arm.com/blog/arm-official-history https://newsroom.arm.com/blog/arm-official-history
- wtetzner 2y agoI seem to have replied to the wrong comment. I meant to reply to the one about Intel threatening Microsoft about emulating x86 on ARM.
- 1000100_1000101 2y agoAh. In that case, I'm not sure what the difference is. Both Rosetta 2, and WoW are translating blocks of code to native, not doing a CPU emulation... I'm wondering if Apple actually has some sort of license to do the translation. Rosetta 2 isn't installed by default. On the PS3, Sony had a pile of media codecs available, and you had to enable each one manually to generate a license key... which I'm sure was to avoid paying for codecs that people aren't using. Rosetta requiring an installation could just be space saving, or could be a sign they're paying a license per install, and avoiding the cost when it's not needed.
- ysofunny 2y agofree instruction sets: this "langauge" should be spoken by all! a public ISA private instruction sets: this is a private matter, restricted to a need-to-know basis. private ISA the main difference is the private one can sneak in magic backdoor instructions, lost in the vastness of a 2^bit_depth space which is better for a languge? to be spoken used and known by many? or to be unkown and obscure? the funky business is that ISAs pictured as "languages" are spoken by microcontrollers; which scrambles the private/public issue
- ginko 2y ago>the main difference is the private one can sneak in magic backdoor instructions, lost in the vastness of a 2^bit_depth space There's nothing keeping an implementation of a public ISA from adding backdoors.
- abdullahkhalids 2y agoI imagine, with knowledge of the ISA, can help one can define a verification algorithm, in which, the CPU is probed with some known inputs to gain confidence that there is no backdoor.
- colejohnson66 2y agoYou would just tailor your backdoor to not trigger unless a certain key sequence is performed.
- cesarb 2y ago> in which, the CPU is probed with some known inputs to gain confidence that there is no backdoor. There are 2^64 possible values for a single register. It's not possible to probe all possible combinations of values for the over 60 user-accessible registers, to find the single combination which, when calling a specific one of the more than 2^30 possible instructions, silently flips a secret "disable all permissions checking" bit.
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- leucineleprec0n 2y agoInstruction set baselines should ideally be well-regulated open standards. They should also be good, and not moronic academic projects running of 32B opcode space because of religious dedication to silly extensions and the uniformity of an ISA for saving pennies on microcontrollers to high performance CPUs. RISC-V in principle is a great idea. Hopefully we’ll get something that’s at the caliber of a well-oiled machine backed by real experience and practical high performance use like Arm V8 and V9 someday that’s a bit more open, but as of right now RISC-V not only isn’t that on a technical level but is fighting some serious fragmentation. https://www.theregister.com/2024/05/29/riscv_messsaging_struggle/ https://www.theregister.com/2024/05/29/riscv_messsaging_stru... And here’s David Chisnall on ISAs, which do matter: https://queue.acm.org/detail.cfm?id=3639445 https://queue.acm.org/detail.cfm?id=3639445
- IshKebab 2y agoI think David Chisnall's article is very good. However I don't think you should oversell the few issues with RISC-V. There are definitely some design mistakes, but overall it is good. I would say as good as ARM (but not as mature yet). Also... consider how successful an insane instruction set like x86 is! The ISA definitely matters for performance, but it clearly doesn't matter that much. Also the uniformity of the ISA is very nice for compilers. Sure in practice you're only ever going to use x1 or x5 for your return address but adding the hard constraint that you can only use those is definitely going to complicate some software. I'm not sure what you mean about fighting fragmentation. I used to think that but I didn't know about the RVA profiles.
- fwsgonzo 2y agoIndeed, I think he's repeating something that is today outdated information. With RVA profiles, we know what desktop-class RISC-V looks like, and that's what people might compare against ARM.
- Vt71fcAqt7 2y agoI don't see why "moronic" was needed there. Also Risc-V has profiles that group multiple extensions together for specific use cases. For example RVA23[0] which requires 64 bit and vector extension among many others. Operating systems like android can (and most likely will) specify that they only support certain profiles.[1] Lastly, ARM is also fragmented between Armv8 and Armv7 which android developers are still supporting. >RISC-V not only isn’t that on a technical level but is fighting some serious fragmentation. Do you have any evidence to support this? Seems like RVA23 will be the first majorly supported extension. All the "high performance CPUs" right now are just dev kits, so I don't see how there can be fragmentation in a market that does not yet even exist. [0] https://github.com/riscv/riscv-profiles/blob/main/src/rva23-profile.adoc https://github.com/riscv/riscv-profiles/blob/main/src/rva23-... [1] https://opensource.googleblog.com/2023/10/android-and-risc-v-what-you-need-to-know.html https://opensource.googleblog.com/2023/10/android-and-risc-v... (note: the blog mentions RVA22 but this has most likely been switched to RVA23 before full Risc-V support lands in Android).
- bdowling 2y agoWould copying an instruction set and ABI to make an interoperable processor and system be fair use in light of Google v. Oracle (2021) [0][1]? [0] https://www.supremecourt.gov/opinions/20pdf/18-956_d18f.pdf https://www.supremecourt.gov/opinions/20pdf/18-956_d18f.pdf [1] https://en.wikipedia.org/wiki/Google_LLC_v._Oracle_America,_Inc https://en.wikipedia.org/wiki/Google_LLC_v._Oracle_America,_.... Edit: Changed phrasing of question. Also, to be clear I think the answer is probably yes.
- hn_acker 2y agoMost likely yes. In Google v. Oracle, the Supreme Court ignored whether software APIs are copyrightable and instead performed a fair use test. Oracle's Java APIs remain under copyright, but Google's use of the APIs were fair use.
- bdowling 2y agoI rephrased the question. The instruction set may be copyrightable, but as in Google v. Oracle, we don't have to answer that question. Even if an instruction set is copyrightable, then under Google, it is probably fair use to copy it for interoperability purposes (e.g., making a compatible processor or emulator). For the actual binary encoding of instructions, there is even less of an argument for copyright protection because the encoding is purely functional.
- layer8 2y agoIt’s certainly (?) legal to implement an emulator for a given instruction set. I’m not sure how implementing a CPU in hardware would be different. What clearly is subject to copyright is the documentation describing the instruction set and its semantics.
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- LegionMammal978 2y agoGoogle v. Oracle was not about interoperability: as the decision presents it, Google copied the APIs for Android specifically because they didn't want false interoperability with desktop Java. Instead, the court found that the use was transformative (bringing Java to a new, distinct platform), insubstantial (the declarations being non-central to the overall implementation), and with little market effect (Sun/Oracle having failed to make its own mobile Java viable). In contrast, reimplementing a copyrighted ISA would quite clearly be substantial and could easily have large market effects. So you'd have to lean heavily into the idea of interoperability to overwhelm the lack of these other factors, or argue that the ISA is not copyrightable per se. Also, even if an ISA isn't copyrightable, you have to watch out for patent rights the owner might have over any part of the ISA.
- jqpabc123 2y agoSoftware should be free --- except the stuff I earn a good living from.
- microtherion 2y agoAlso known as "commoditize your complements".
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- ribit 2y agoI fully support the idea of open instruction sets. I am not as much sold on the idea of cookie-cutter one-size-fits-all instruction sets. RISC-V is very nice for teaching CPU basics, and it is a great fit for tiny cores or specialized microcontrollers. Unfortunately, since it has been designed for simplicity it appears that it makes it harder building high-performance cores. RISC-V philosophy for high-performance OoO cores relies on instruction fusion, and thus would require the compiler to emit fusion-friendly sequences for best performance - and these sequences might differ from CPU to CPU. To me this seems to go against the very idea of common open ISA. We already see quite a lot of fragmentation and I fear it will only get worse as time goes on. More complex instructions that combine multiple processing steps would help, it seems that the core RISC-V community is opposed to that idea out of purely ideological reasons.
- camel-cdr 2y ago> More complex instructions that combine multiple processing steps would help, it seems that the core RISC-V community is opposed to that idea out of purely ideological reasons Thats not true, the Scalar Efficiency SIG is currently working on such an extension. See this spreadsheet of discussed instructions: https://docs.google.com/spreadsheets/u/0/d/1dQYU7QQ-SnIoXp9vVvVjS6Jz9vGWhwmsdbEOF3JBwUg/htmlview https://docs.google.com/spreadsheets/u/0/d/1dQYU7QQ-SnIoXp9v... and charter: https://github.com/riscv-admin/riscv-scalar-efficiency/blob/main/charter.adoc https://github.com/riscv-admin/riscv-scalar-efficiency/blob/...
- ribit 2y agoI remember last year (?) Quancomm proposing an ISA extension that brings ARM-like addressing modes and paired stores to RISC-V, and the community reaction being very negative. Happy to hear that there are now initiatives to streamline these proposals and make RISC-V a better fit for high-performance CPUs. I am looking forward to future developments!
- camel-cdr 2y agoThe negative responses were, because Qualcomm wanted to remove the C extension from the application profiles. Qualcomm prefered a strict 32-bit instruction set, with potentially 64 bit naturally aligned instructions. RISC-V is designed for 16, 32, 48, 64 bit instructions that are 16 bit aligned, and retroactively changing that wouldn't have been a good decision. Both sides of the argument agreed that both options are resonable and don't hinder high performance designs. Qualcomm seems to have accepted this now, as they e.g. proposes 48 bit instructions with larger immediats.
- brcmthrowaway 2y agoWhatever happened to RISCV, wasnt it the big new thing like AI and web3?
- brucehoult 2y agoRISC-V currently has an installed base of around 15 billion CPUs, increasing at a current rate of maybe 4 billion a year. The first half a dozen relatively low performance [1] brands and models of laptops and tablets have come out in the last year, as has a workstation with 64 OoO cores running at 2.0 GHz, 64 MB L3 cache, 128 GB RAM. By the end of the year RISC-V SoCs will be shipping with 2x the IPC they had at the start of the year, and also significantly higher clock speed. 8 or 16 cores will be the norm, vs 4 at the start of the year. You're going to see RISC-V smart phones by around 2026 or 2027. [1] something like late Pentium III per core, but quad core.