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FPGA Architecture for Deep Learning: Survey and Future Directions
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- m3kw9 3y agoDangs got some work cut out for him tonight
- ronsor 3y agoI've never seen so much spam in a thread before.
- dragontamer 3y agoIts across everything on the frontpage. Hundreds of spam links. It looks very much like a concerted attack of some kind. The spam seems quite ineffective, so I'm wondering if the "real" attack is trying to get the moderators to hell-ban a legitimate person to silence them or something. I dunno, its really weird. Its hard for me to take this spam at face value, I can't imagine that this website is a good target for such spam. Its clearly just here to annoy the moderators and make them tired vs... something. Reminds me of Starcraft Muta Harass: you're attacking the APM and attention-span of the opponent, not actually trying to straight up win with Muta. If that makes any sense.
- mschuster91 3y agoOr it's some kind of weird-ass SEO campaign (not that it'll work, dang has implemented rel=nofollow a few months ago). Man, I've been on HN for >11 years now, literally never saw a spam campaign this intensive.
- blackeyeblitzar 3y agoGiven they all link to Discord, I wonder if @dang should consider contacting their abuse team to investigate and take down those channels.
- Rexxar 3y agoMaybe it's exactly what they want (I didn't check the links). Maybe they want to make someone they don't like banned.
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- woopsn 3y agoReconfigurable logic may be used to implement fairly small models, in applications where they're already employed and adding a coprocessor specifically for ML is either infeasible or doesn't make sense. As the paper mentions, you need hard logic blocks for arithmetic (if not floating point), and these are always in short supply. In DSP applications I've worked on we used the fpga for timing and i/o, to control jitter and sample from many ADCs in parallel - but apart from some filtering then ran the numbers on an adjacent non-reconfigurable core. You can get huge chips with a lot of hard logic built in, but they're relatively expensive compared to fpga + traditional coprocessor with shared memory. The high end application specific chips are shockingly expensive - worse than GPUs because there is comparatively little market for them. We had one evaluation board that was like $100K iirc.
- ZoomerCretin 3y agoYep. Google has TPUs, and AMD/Nvidia/Intel/Apple/Qualcomm all have tensor coprocessors now. From a CPU or GPU to an FPGA, the cost/benefit is huge. With every device having tensor cores, not so much. ASIP and ASICs are likely the way to go, at least for common operations like matrix multiplication.
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- ZoomerCretin 3y agoI'm glad to see this is being studied. I did a brief half-semester project summarizing the usefulness of accelerators after the death of Dennard's law and Moore's law (this was when Intel was still pushing out incremental improvements on 14nm). The short summary is that accelerators offered substantial performance per watt improvement, at the cost of longer development timelines, cost of manufacturing in the case of ASICs and ASIPs, and the inability to fit large algorithms on FPGAs. Though Microsoft found a way to daisy-chain FPGAs for Bing's page rank, it just didn't produce the order-of-magnitude improvement necessary to justify moving to FPGAs. With smaller algorithms or bigger FPGAs or occasional operation offloading (like what we do now with TPUs and GPUs), they could be good candidates for accelerators. Of course the real killer is how easy it is(n't) to develop for them. AMD offers much better performance per dollar than Nvidia, but of course their poor drivers make using their hardware a fool's errand. RADs sound like a good idea. We should be making reprogrammable hardware available and easy to use for everyone.
- 15155 3y ago> AMD offers much better performance per dollar than Nvidia, but of course their poor drivers make using their hardware a fool's errand. I would never use their IP or drivers, but Xilinx hardware is top notch. What drivers are you using? XRT?
- buildbot 3y agoBrainwave is/was very successful? Still serving your searches! (I work on one of the teams that came out of brainwave, not with them directly) https://www.microsoft.com/en-us/research/project/project-brainwave/ https://www.microsoft.com/en-us/research/project/project-bra... https://www.microsoft.com/en-us/research/publication/a-configurable-cloud-scale-dnn-processor-for-real-time-ai/ https://www.microsoft.com/en-us/research/publication/a-confi... https://www.microsoft.com/en-us/research/blog/a-microsoft-custom-data-type-for-efficient-inference/ https://www.microsoft.com/en-us/research/blog/a-microsoft-cu... -> This led to the OCP MX work: https://www.opencompute.org/blog/amd-arm-intel-meta-microsoft-nvidia-and-qualcomm-standardize-next-generation-narrow-precision-data-formats-for-ai https://www.opencompute.org/blog/amd-arm-intel-meta-microsof...
- zachbee 3y agoThe big challenge when it comes to using FPGAs for deep learning is pretty simple: all of that reprogrammability comes at a performance cost. If you're doing something highly specific that conventional GPUs are bad at, like genomics research [1] or high-frequency trading [2], the performance tradeoff is worth it. But for deep learning, GPUs and AI ASICs are highly optimized for most of these computations, and an FPGA won't offer huge performance increases. The main advantage FPGAs offer is being able to take advantage of new model optimizations much earlier than ASIC implementations could. Those proposed ternary LLMs could potentially run much faster on FPGAs, because the hardware could be optimized for exclusively ternary ops. [3] Not to toot my own horn, but I wrote up a blog post recently about building practical FPGA acceleration and which applications are best suited for it: https://www.zach.be/p/how-to-build-a-commercial-open-source https://www.zach.be/p/how-to-build-a-commercial-open-source [1] https://aws.amazon.com/solutions/case-studies/munich-leukemia-lab/ https://aws.amazon.com/solutions/case-studies/munich-leukemi... [2] https://careers.imc.com/us/en/blogarticle/how-are-fpgas-used-in-trading https://careers.imc.com/us/en/blogarticle/how-are-fpgas-used... [3] https://arxiv.org/abs/2402.17764 https://arxiv.org/abs/2402.17764
- jacobgorm 3y agoI was part of a startup that did ternary CNNs on FPGA in 2017. It involved a ton of nitty gritty work and massive loss of generalit, and in the end a Raspberry Pi could solve the same problem faster and cheaper.
- adultSwim 3y agoWhat about FPGAs as a means to experiment in ML and hardware architectures?
- kadushka 3y agoThere are two other problems with FPGAs: 1. They are hard to use (program). If you're a regular ML engineer, there will be a steep learning curve with Verilog/VHDL and the specifics of the chip you choose, especially if you want to squeeze all the performance out of it. For most researchers it's just not worth it. And for production deployment it's not worth the risk of investing into an unproven platform. Microsoft tried it many years ago to accelerate their search/whatever, and I think they abandoned it. 2. Cost. High performance FPGA chips are expensive. Like A100 to H100 price range. Very few people would be willing to spend this much to accelerate their DL models unless the speedup is > 2x compared to GPUs.
- mikewarot 3y agoMy pet project is to take these ideas and go to the logical end, arriving at a systolic array I call a BitGrid. It's a Cartesian grid of 4 bit look up tables, with bits to/from each neighbor. This allows each output to be independent, maximizing utilization. To solve timing issues, each cell would be clocked, with 2 phases for the grid, in a checkerboard pattern. This makes all inputs stable, and timing deterministic. Unlike an FPGA, latency is not the primary limit of performance, as everything is thus pipelined. I wrote a simulator, and started learning VHDL in order to program an FPGA board I bought for prototyping the concept. My eventual goal is an ASIC through tiny tapeout. The big software hurdle is compiling expressions into a directed graph of bitwise operations. Because data only travels to the neighbors, all the lines in a chip are short, and it should be possible to use far fewer metallization layers in an actual chip than a CPU for example.
- sitkack 3y agohttps://tinytapeout.com/ https://tinytapeout.com/ now lest you purchase additional tiles for $50, each tile supports about 1k digital logic gates. Next one closes June 1. https://tinytapeout.com/faq/ https://tinytapeout.com/faq/ You might enjoy this talk from the last Latchup on Wave Pipelining https://fossi-foundation.org/latch-up/2024#riding-the-wave-building-wave-pipelines-in-fpgas https://fossi-foundation.org/latch-up/2024#riding-the-wave-b... https://www.cs.princeton.edu/courses/archive/fall01/cs597a/wave.pdf https://www.cs.princeton.edu/courses/archive/fall01/cs597a/w...
- ooterness 3y agoWhat you're describing is a cellular automaton, in the same vein as of Conway's Game of Life. You can do lots of interesting things with those, but it's emphatically not where I'd start for a flexible computing platform. Why not go the extra mile, and make each tile a small CPU? There's a Zachtronics have called TIS-100 with this premise. https://store.steampowered.com/app/370360/TIS100/ https://store.steampowered.com/app/370360/TIS100/
- mikewarot 3y agoBecause each cell has it's own state, and 64 bits of "program" (16 bits in each of the 4 LUTs), it's unlike the game of life, where the rule is the same for each cell. I looked at a lot of choices for architecture, and wanted to allow data paths to cross without conflict, and the 4 in/4 out choice worked best without going too far. Someone did work out how you could run the game of life on a BitGrid, it's in the Esoteric Languages wiki https://esolangs.org/wiki/Bitgrid https://esolangs.org/wiki/Bitgrid I see it as something like a Turing machine, a bit less abstract, and much, much faster at computing real results. I hope it can democratize access to PetaFLOPS. The question I can't seem to find an answer to is simple... how much power does a 4 bit in/out set of LUTs with a latch take statically? How many femtojoules does it take to switch? If those numbers are good enough, it's entirely possible that really fast compute is on the table of possibilities. If not, it's another Turing machine.
- WanderPanda 3y agoIs there any small risc-v soft-core with big ass SVE (scalable vector extensions)? I would like to play around with them but the only option seem to be cloud instances like gravitron and small (128bit) like the licheerv nano (c906) which also seems to only support a beta version of the standard.
- camel-cdr 3y agoYou seem to be confusing two different things: gravitron: has ARM SVE extension licheerv nano: has RISC-V Vector extension Both ARM SVE and the RISC-V Vector Extension (RVV) are vector length agnostic, but quite different in their design. Since RISC-V allows for open source implementations, there are a few projects working on RVV implementations. Check out the t1 project, they implement a configurable RVV implementation, that is supposed to be driven by a small scalar core, e.g. RocketChip. [0] There are configurations for vector length of 512-bit to 16K bit. Connecting it to RocketChip isn't officially supported just yet, and it uses the spike emulator for the scalar part. They offer a pre-build docker environment, so you can play around with the RTL simulation via "docker run --name t1 -it -v $PWD:/workspace --rm ghcr.io/chipsalliance/t1-machamp:latest /bin/bash" This drops you into a shell, and you can start simulating a 1K vector length processor, with "ip-emulator --no-logging -C yourProgram", see the tests/ director for example code. At least in theory, but there might still be a few bugs. [0] https://github.com/chipsalliance/t1 https://github.com/chipsalliance/t1
- pjmlp 3y agoMeanwhile others are trying to bring back analog CPUs for similar kinds of workloads, it is going to be interesting which ones end up winning in the long run. For example, https://mythic.ai/products/m1076-analog-matrix-processor/ https://mythic.ai/products/m1076-analog-matrix-processor/
- hoseja 3y agoHave them self-modify.