7 ms·
With durability claims of > 10 million write/erase cycles this is not going to compete with DRAM, which needs to endure trillions of write/erase cycles in its
by tromp 3y ago
With durability claims of
> 10 million write/erase cycles
this is not going to compete with DRAM, which needs to endure trillions of write/erase cycles in its lifetime.
Unless they grossly underestimated its durability, a name like UltraFlash would seem more appropriate?!
- arc-in-space 3y agoTrillions of cycles, what? How can that be? Maybe I'm confusing something, but to reach a trillion cycles in, say, a year, would take overwriting all your memory 30 times a millisecond. That doesn't sound right? Or is that trillions of any writes and erases?
- tus666 3y agoLifetime of microeletronics is often quoted at around 30 years. So that's once a millisecond. For a refresh cycle that does not seem extraordinary.
- Etherlord87 3y agoI started to think about flipping a single bit in some process a million times per frame inside some loop, but that could only be done in cache… Still if you only changed the state of the memory once per frame, you would do it in RAM, not in cache. At 1000 FPS (we should consider the worst scenario even if rare) that's 3 hours of playing a game to reach 10 800 000 reads/writes. Now question is what happens if that bit gets damaged, perhaps the memory just disables it as damaged, and uses another bit for this memory address from now on. Perhaps it makes the ultra ram slower over time as more bits (sectors) get damaged?
- Cort3z 3y agoDDR ram is refreshed every 64ms (varies by DDR generation and specific chips). Branch Education has an excellent video on this named "How does computer memory work?"[1]. It would still take an exceedingly long time to reach a trillion, but it's still pretty frequent. [1](https://www.youtube.com/watch?v=7J7X7aZvMXQ https://www.youtube.com/watch?v=7J7X7aZvMXQ)
- xnorswap 3y ago1 trillion * 64ms is over 2000 years, I think it's unlikely that there's any DDR RAM that old.
- Cort3z 3y agoFrom just refreshing. You generally do other stuff than refresh the ram too.
- xnorswap 3y agoOf course, but it's still a huge order of magnitude difference to get to trillions.
- archontes 3y agoLike, say, serving a million MMO users?
- deleted 3y ago[deleted]
- MayeulC 3y agoYou don't need to refresh non-DRAM memories though. I agree that some regions risk being R/W more than others, so memory controllers should indeed perform some kind of wear levelling, but otherwise I find it hard to imagine trillions of overwrites across GBs (or TBs) of data. 1e6 cycles is definitely doable, and on the low side, even for flash devices. 1e9 is pretty good for general-purpose memories, and few applications require 1e12. Not even SRAM or DRAM have unlimited endurance, due to physical wear. It's hard to find a source on this, but I would probably hand wave it at around 1e15 cycles for DRAM? This would be 30 years of operation for one access every microsecond.
- Kirby64 3y agoIn comparison, 10 million would mean less than a day if it was refreshed every 64ms. Even a billion would mean only 2 years worth of cycles. I think a trillion, or at very least 10s-100s billion is the correct amount of cycles for RAM.
- jepler 3y agoIf you have to design for pathological workloads, absolutely you can write to a location in main memory 30 times per millisecond. Lots of non-pathological workloads might write to a memory location every millisecond, such as a game with a 4-pass renderer running at 240Hz.
- tromp 3y agoI was thinking of overwriting just a few words of memory over and over again, which DRAM can endure for decades.
- mattclarkdotnet 3y agoEven at 1GHz, a trillion (10^12) writes is only 1000 seconds of work for a modern CPU. OK latency is a thing, so multiply by 10 and it takes a day. This is for DRAM where cells are individually addressed. For flash with wear levelling the numbers of course get bigger.
- jandrese 3y agoIn practice a memory location being written to that heavily will never escape the cache unless you are doing something exceptionally weird.
- DoctorOetker 3y agodoesn't C have keywords like volatile to insist reading from RAM?
- vlovich123 3y agoI would seriously doubt there’s many instances of writing to a single volatile memory location at 1ghz (excluding benchmarks).
- aidenn0 3y agoVolatile requires it emit instructions that access the object. So if the object is in RAMA, it will emit memory access instructions. However, on modern CPUs, that will still hit the cache. You need to either map in the memory as uncached, or flush the caches to force a memory access
- pbalcer 3y agono, that won't work. You'd have to clflush after every store. And even then, the cacheline might only ever get to the write pending queue (wpq) - and that you can't control.
- pezezin 3y agoModern DRAM doesn't address individual cells. For both DDR4 and DDR5 the minimum burst length is 64 bytes, the width of a cache line of most CPUs.
- pmontra 3y agoThe clock frequency is GHz, which is a trillion cycles per seconds. There is at least one cache layer between the CPU and the RAM but we are in the same ballpark. And yet it's OK for the typical lifetime of our computers.
- tuatoru 3y agoYeah, potentially dead in ten milliseconds with a pathological workload.
- Findecanor 3y agoThat's about the same durability as Intel Optane had, so the first thing it could be would be to replace Optane where it has been used. Optane did inspire a lot of R&D into persistent data structures, databases and file systems that started to challenge the traditional model of local memory and persistent storage. IMHO, a few of those projects were a little bit overoptimistic, and used NVRAM as DRAM without many restrictions. For NVRAM to be viable, I think it still needs to have overprovisioning, wear levelling, memory-protection and transactions, provided by hardware and/or an OS but not necessarily with traditional interfaces. It is mostly a matter of mapping it CoW via a paging scheme instead of directly, and it will still be at near-DRAM speed.
- zozbot234 3y agoThat's basically the equivalent of a Flash Translation Layer, and having it removes the original selling point of making fsync() a no-op. At that point, persistent memory's only advantage over existing non-volatile storage is possibly higher performance.
- Findecanor 3y agoTo hell with fsync(), I'd want a proper commit()! ;) The performance is so high that the assumptions that had led to the old file system interfaces don't apply any more. There is opportunity for something better.
- londons_explore 3y agoWear levelling on RAM isn't in use today to my knowledge, but I don't think it is technically impossible. You would probably go for some approach where most memory addresses are direct-mapped, and then the few that have been written most are redirected to new addresses. The reading of the direct-mapped addresses would be super fast, since you can do the read in parallel with the lookup in the remapping table (just to check that this is a direct-mapped address). Reads of non-direct mapped addresses might take a couple of extra cycles, but that doesn't matter because they are very rare. To do any of that, CPU memory controllers need to be able to handle per-request variable-latency RAM, which to my knowledge today they do not, although it would not be a big redesign to add.
- ahoka 3y agoWear leveling RAM would be trivial with any MMU from the last 40 years. You can just fault on the write and do your wear leveling in the fault handler. This is how virtual memory already works.
- londons_explore 3y agoIndeed, and this is how "badram" on Linux works.
- Tuna-Fish 3y agoNo, you would keep a write counter for every (4kB) DRAM page, and have the OS move the virtual page to new physical one if the write count of a page grows much higher than the average.
- vlovich123 3y agoThat assumes you still have DRAM. Since this is faster and higher capacity than RAM, it’s potentially viable as a RAM replacement. In that case, you wouldn’t have anywhere to store the counters (but presumably in that case you wouldn’t need to either). I’m not sure you’d need to have a write counter when this replaced RAM though even if this didn’t have the same write endurance. For storage nodes, there’s no value in RAM outlasting storage. And this already has better write endurance than NAND. So on a storage node, you could easily imagine using this as RAM as the number of erases is going to be dominated by storage activity rather than ancillary memory writes managing the storage.
- dan-robertson 3y agoIf the latency claims turn out to be true, it could still be worth it in various cases, eg with a bit of effort to reduce the number of writes you could get a big hashtable that you initialise once a day or so that gives really fast lookups.
- agumonkey 3y agoNoob question, aren't the trillions of cycle including 'refreshing' read/write that wouldn't be necessary with persistent memory ?
- adrian_b 3y agoYou can trivially exceed one million write cycles in only a second with a modern CPU, just by incrementing a shared counter (which cannot be cached).
- adwn 3y ago> just by incrementing a shared counter (which cannot be cached) That's not true, a shared counter (i.e., an atomic integer) is cached – in fact, there's no guarantee that its value is ever written back to system RAM. You're probably thinking of non-cacheable memory: the kernel can set the MMU attributes of a memory page such that the CPU will avoid the cache when it accesses addresses in that page. This is completely independent of atomic accesses on memory locations [1]. [1] At least typically – there may well be CPUs which disallow atomic accesses on non-cacheable memory.
- SonOfLilit 3y agoI assume by "which cannot be cached" he meant "which is in a page configured as non-cacheable in the MMU", i.e. exactly what you said
- jackmott42 3y agoI would buy RAM yearly for 10x latency improvement!
- mejthemage 3y agoCan you imagine the consumer backlash? RAM is not easily removable in most of today's electronics. So replacing RAM once a year actually means replacing all your devices once a year.
- benj111 3y agothings that dont last long are replaceable though. no one complains about not being able to replace the processor in their phone because it 'never' breaks. batteries on the other hand do, and to varying degrees are replaceable.
- adolph 3y agoI've been impressed by the growing capabilities of the device fixing community. Replacement of BGA components is more attainable than one might think. https://www.youtube.com/watch?v=X7C_hdJsY4Y https://www.youtube.com/watch?v=X7C_hdJsY4Y I think for my kids I may have them skip traditional through wire soldering for SMD with hot air and toasters. https://hackaday.io/project/27900-reflowduino-wireless-reflow-controller-ecosystem https://hackaday.io/project/27900-reflowduino-wireless-reflo...
- crote 3y agoThat really depends on your use case, doesn't it? Assuming a typical 5-year lifecycle, 10 million writes means 1 write every 15 seconds. That's more than enough for executable code, CDN content, or a database index. I can definitely see systems with 75% UltraRAM for read-heavy data and 25% traditional RAM for write-heavy pages acting basically as L4 cache.
- moconnor 3y agoPerfect for LLM weights though.
- IanCal 3y agoThey have tested it to 10 million cycles with no degradation, so that's where that figure comes from. It's not 10e7 before failures or 10e7 before failures at some particular rate. The assumption is it's somewhere higher than this but you can't tell without more testing. > The process was repeated five times, resulting in a little over 10^7 program/erase cycles applied to the device. As can be clearly seen in Figure 4d, there is no degradation of the ∆IS-D window throughout these tests, meaning that the endurance is at least 10^7. https://onlinelibrary.wiley.com/doi/epdf/10.1002/aelm.202101103 https://onlinelibrary.wiley.com/doi/epdf/10.1002/aelm.202101...
- runeks 3y agoHmm. If this memory is faster than DRAM, wouldn't it be quick to test, say, ten trillion write/erase cycles? Why stop at 10M? Is the erase operation really slow?
- idiotsecant 3y agoProbably a case of don't ask questions you don't want answers to.
- dahfizz 3y agoThe paper says they tested the durability of the ram with a 5ms program-read-erase-read loop. Meaning each time they program-read-erase-read, it takes 5 milliseconds. Ten trillion cycles would take over 150 years. I'm guessing a silicon lab doesn't have "the rest of the computer" that would allow them to run this ram at full speed constantly. This UltraRAM isn't something they can just slot into their motherboard.
- DoctorOetker 3y agoThese labs have their custom structures synthesized, adding a small circuit specifically for endurance testing would be trivial compared to what they have achieved designing and implementing the structures they have.
- Tuna-Fish 3y agoSome of the researchers believe that the durability is actually unlimited, but they haven't been able to prove it yet.
- benj111 3y agoWhy does it need to directly compete with dram? The current set up is based on separating volatile and non volatile memory and adding caches to paper over the slowness. Caches are getting bigger and bigger because of the huge speed disparity. I think you underestimate how much of a game changer this could be. This is persistent and fast. If this takes off, and it does only last 10s of millions of cycles, just use cache for fast changing things and ultraram for everything else. If it lasts trillions of cycles, it potentially would completely change pc architecture. It was the 80s when we had ram/rom that could keep up with the processors of the day. This potentially gets you an instant on computer, no need for caches, no need for memory for the graphics card, no separate hard drives. Just one big simple bucket of bytes for everything.