8 ms·

AMD Introduces World’s Largest FPGA-Based Adaptive SoC for Emulation

110 points by hasheddan 3y ago

VoxPelli 3y ago
So, will CoreScore get a new leader? https://corescore.store/ https://corescore.store/
- sitkack 3y ago
  That would have been a great marketing stunt!
guepe 3y ago
I'm close to this (I work in emulation) and that chip IS awesome. It is the first fpga really designed with emulation in focus.
- currio 3y ago
  Can you please tell us, who don't work in the field, what makes this chip awesome
  - Taniwha 3y ago
    This chip is for other chip designers - basically when doing chip design you want to make a product that works first time (or explain to your boss why he should spend hi 6 figures on a spin) - so you test test test ... what this is for is that a chip team will take their verilog design, compile it into luts and load it up here, it will likely run at ~10% of your designed speed - the alternative is compiling your verilog to code and have it run at 0.1% - 100x more testing
- adwn 3y ago
  > It is the first fpga really designed with emulation in focus. Not really. In each generation of devices, Xilinx had one focused on emulation for while now: huge number of LUTs, huge number of general purpose IOs, relatively few DSP elements, a moderate amount of block RAM. Before this monster, it was the Virtex Ultrascale+ VU19P, and before that, the Virtex Ultrascale XCVU440, and before that, the Virtex 7 XC7V2000T.
- jonny_eh 3y ago
  What does "emulation in focus" mean?
- Lramseyer 3y ago
  Since so many people are asking what "emulation" is, I'm going to respond to the parent comment instead: "Emulation" refers to emulation of chip designs. When a chip has billions of transistors that are all connected to each other to perform higher level functions, you need to test out designs in order to make sure those higher level functions actually do what you expect them to. Most modern chip designs (at least the digital portions of them) are designed using what's called a Hardware Description Language or "HDL" such as System Verilog or VHDL. It's somewhat similar to traditional programming, except threads are nonexistent, so it's essentially an unholy bastardization of a markup language and a programming language. But I digress... These functions are then synthesized into their low level building blocks such as buses, gates, and registers, and are placed and laid out on a chip. Going back to the part about billions of transistors; as you might imagine, testing of such designs must be rigorous and thorough. Only problem is that it's really, really computationally intensive. There are 2 ways of doing it: Simulation (CPU Based) and Emulation (FPGA Based) Simulation is slower, but yields more data like waveforms and whatnot (though you can get waveforms with emulation, but there are more limits.) Also, simulation takes less time to compile, since there's no place and route step. I should also point out that there are 4 key simulation levels: Simulation Model (usually compiled C code) RTL Simulation (Functional level simulation) Gate level Simulation (simulating the individual gates) and physical simulation (where the transistors and trace routing are all accounted for.) Each level being roughly an order of magnitude more computationally intensive than the previous. Most time and engineering effort is spent on RTL level simulation, which is what can, and is often emulated on an FPGA, and why this product is so relevant to hardware designers.
  - Aromasin 3y ago
    If anyone wants to dive a bit deeper into this, I always like to point towards: https://fpgaemu.readthedocs.io/en/latest/ https://fpgaemu.readthedocs.io/en/latest/ If you're a software engineer interested in the hardware side of things, there's a great article for explaining the difference between the programming methodologies: https://nandland.com/lesson-7-what-every-software-programmer-needs-to-understand-about-hardware-design/ https://nandland.com/lesson-7-what-every-software-programmer... To add some extra context, usually when a hardware designer is testing something on an FPGA they'll be testing just one specific IP core (a reusable unit of logic, cell, or integrated circuit layout design that is the intellectual property of the company). Let say, an Ethernet MAC for example. You don't necessarily need a chip like the one in the article to test that. You basically validate what all the inputs and outputs of said IP are going to be; you know that some signals are going to the PCS/PHY and some to a processing core/memory, and provided everything is done correctly then you should be able to slot the IP into your final chip design and everything works. That's not always the case though, which is why some companies end up have many stepping's (revisions of the semiconductor photomasks used to pattern an integrated cirucit). Many companies, my own included, make a business out of designing and selling these IPs to other companies without ever really knowing what the end customer wants to do with it. We just tell them what signals to put in, and what to expect out. With some of the larger FPGAs, you can connect many multiple IPs together and emulate the whole IC, but it depends on scale. You can easily emulate a whole Intel 4004 chip, but you're not fitting a whole Apple M1 design on a single device. With the chip in the article though, we're a step closer to that. Generally you might have 16+ FPGAs on a single PCB to test that scale of functionality. Even that's not a "true" test of a whole IC though, because of the delay in chip-to-chip communication. You might send your design to the foundry and find you've failed on timing. An Agilex 7 M-Series, one of the larger FPGAs in the Intel portfolio, has 3.9M LEs. This chip has what looks to be 18.5M. It's not a 1:1 comparison because they have different architectures, but you get a rough idea of the jump in scale here. This Versal Premium chip will be a massive boon to the likes of Apple, Tesla, NVIDIA, etcetera, because they can potentially emulate the entire chip function on a single die, meaning less steppings to get production quality silicon.
deleted 3y ago
[deleted]
crote 3y ago
For those wondering what an "Adaptive SoC" is supposed to be: It is essentially an FPGA packed together with some ARM cores and interconnects into a single chip.
gjsman-1000 3y ago
For context, "emulation" here is not referring to emulation for video game systems, but for SoC Designers. It could potentially be used for that though if the cost wasn't likely very prohibitive like most FPGAs (and frankly, the VP1902 price tag is likely to be enormous).
- cogman10 3y ago
  And to be clear, this is a xilinks product. I didn't realize they were purchased by AMD, but they are a old FPGA manufacturer. This isn't "FPGA in your CPU" sort of thing but rather just a generational improvement on existing products.
  - tiffanyg 3y ago
    Yup, here's info through Xilinx website (without some of the confusion possible in the current comparatively early stages after acquisition): https://www.xilinx.com/products/silicon-devices/acap/versal-premium/vp1902.html https://www.xilinx.com/products/silicon-devices/acap/versal-... Seems there's still a relative dearth of 3rd party articles, but probably will see at least some more fairly quickly (w/ lifting of embargo etc.).
  - iamflimflam1 3y ago
    I did my final year project using a Xilinx FPGA back around 1992. We put some image processing algorithms for fingerprint processing onto it for adaptive thresholding and line thinning. There was a lecturer who was very into hardware software co-design but had got quite disillusioned with it as general purpose CPUs just kept getting faster and faster.
    - photonbeam 3y ago
      Good news then, growth in speed for single threaded has been slowing
kcmastrpc 3y ago
So is this a successor to the DE-10 Nano (the board the MiSTERFPGA project is based on)? (after looking at corescore probably not, as it'd be way too expensive. that being said, the DE-10 Nano is getting old, are there any potential successors coming)?
- Foobar8568 3y ago
  DE-10 nano is an Intel (Altera) board based on a Cyclone V, I don't think there has been any mindful updates in this price range at Intel.
- asguy 3y ago
  There are many already available, e.g. ZedBoard, someone just has to do the work to target these other boards and their peripherals/layout.
  - MegaDeKay 3y ago
    Nothing is really comparable to the DE-10 Nano's combination of capacity, embedded ARM cores, memory, HDMI scaler, and (most importantly) price. The ZedBoard fails the last test: it is a fair bit more expensive than the Nano. I am keen on the MiSTex project though. The plan is to come up with something that is more flexible than MiSTer to support different targets. So for example, you might be able to target a simpler core to a simpler device and vice versa. https://github.com/MiSTeX-devel https://github.com/MiSTeX-devel https://github.com/enjoy-digital/litex https://github.com/enjoy-digital/litex
    - postalrat 3y ago
      Is there any chance mister could be made to run on pano logic g2 or others? Those are pretty cheap but aren't made any more.
    - asguy 3y ago
      > and (most importantly) price. … OP didn’t mention they were optimizing for price. Some might say it makes sense to optimize for availability, recent updates to hardware software stack, etc.
jhallenworld 3y ago
https://www.theregister.com/2023/06/27/amd_versal_fpga_emulation/ https://www.theregister.com/2023/06/27/amd_versal_fpga_emula... 77 mm x 77 mm package (a bit larger than my old Pentium Pro).. I'm amazed they have any yield for a chip this large at 7 nm. 18 M LEs. 6864 DSPs. 6865 balls. How long does place and route take? $57K for the smaller VP1802.. https://www.digikey.com/en/products/detail/xilinx-inc/XCVP1802-2MSELSVC4072/18627087?utm_source=findchips&utm_medium=aggregator&WT.z_cid=ref_findchips_standard&utm_campaign=buynow https://www.digikey.com/en/products/detail/xilinx-inc/XCVP18...
- pclmulqdq 3y ago
  The last generation was pushing 12 hours on some of my computers. I assume that if you pay for a top-of-the-line server, you can get one of these done in 4-6 hours or so.
  - aseipp 3y ago
    UltraScale+ you mean? Well, the real question is P&R time at some utilization, right? We were easily doing 14hr P&R times on fairly utilized US+ chips like, 5+ years ago. We probably could have improved this in a number of ways, though. I'd honestly think that if you just want to throw money at it, those absurdly-overclocked gamer rigs that can hit sustained +5GHz boosting on just a few cores would be better if you want the fastest P&R times? Cloud servers will probably have more RAM and memory bandwidth but you can shove 128GB of RAM in the 13900K, memory requirements are relatively easy to meet IMO. Synthesis can definitely scale with some more cores in Vivado (OOC synth) but P&R never seemed to scale beyond what you can just get in a desktop. YMMV I guess.
    - pclmulqdq 3y ago
      Yeah, I meant Virtex UltraScale+ parts. I hear that there is a small cottage industry of people overclocking Threadripper workstations for FPGA synthesis, because the memory bandwidth is actually the primary limiting factor (and the Threadrippers have the same kind of turbo capability as the gaming rigs). I assume that the "x3D" chips help a lot, but I don't know.
monocasa 3y ago
So question: my understanding was th atat one point the cadence hardware emulators weren't FPGA based at their core, but instead custom chips with a sea of little one bit processors that only knew about logic ops (with some FPGAs for interchip routing). Is Cadence using FPGAs for logic now too?
- wmf 3y ago
  It looks like they have two versions: "Palladium Z2 emulation based on a new custom emulation processor offers fastest, most predictable compiles and most comprehensive pre-silicon hardware debug capabilities Protium X2 prototyping based on latest Xilinx UltraScale+ VU19P FPGAs offers highest performance and fastest bring-up times for pre-silicon software validation of billion-gate designs" https://www.cadence.com/en_US/home/company/newsroom/press-releases/pr/2021/cadence-unveils-next-generation-palladium-z2-and-protium-x2-syst.html https://www.cadence.com/en_US/home/company/newsroom/press-re...
- throwaway280382 3y ago
  Yes. Cadence now has two products. One is custom chip based emulator. Another is FPGA based. I worked on the first version of FPGA based emulator.
zackmorris 3y ago
Finally! I've waited 25 years for something like this, which totally derailed the career I had envisioned for myself. I might even lose the option of making fun of all new chips for providing marginal performance increases for exponentially growing complexity, and have to find a new shtick. A few predictions/concerns: * I can't find a price, so I'm predicting that it will be over $1,000 which will prevent it from going mainstream (and also be ~10 times more expensive than it should be). * There will be poison pill(s). Maybe flash memory that can only be written 1000 times, preventing its use for evolutionary hardware and genetic algorithms. Maybe the place-and-route software won't be good enough to prevent short circuits, so certain configurations will burn up. Maybe some aspect of the software will be proprietary and/or encumbered by patents, preventing hobbyists from thinking outside the box and "getting real work done". * Any dedicated hardware like memories, ALUs, etc may be misaligned for various use-cases. I just want an array of RISC-V, Arm, DEC Alpha, PowerPC 601/603, something like that, starting with 2 and topping 100 or 1000 cores eventually. So where I'll need memories near CPUs, something in the FPGA will lack the interconnect to allow that. I hope I'm wrong about any or all of these. Price I can live with, as long as economies of scale or competition kick in and eventually deliver something under $1,000. The rest of it.. eh, I'm not holding my breath. I've been underwhelmed by all previous FPGAs, but maybe they didn't count. Maybe this is something new that finally manifests the original vision of what FPGAs could be.
- adwn 3y ago
  > I can't find a price, so I'm predicting that it will be over $1,000 Try 50x to 100x that at quantity=1. This is not a hobbyist device: this FPGA is the largest you can get on, and it's tailored to the needs of companies that spend 7-9 figures on the verification and validation of their ASIC projects. > Maybe this is something new that finally manifests the original vision of what FPGAs could be. Even small to mid-sized modern FPGAs have far surpassed the "original vision of what FPGAs could be".
  - zackmorris 3y ago
    You're right, and in fairness I haven't used an FPGA or VHDL since the 90s. I spent the 2000s in destitution and the 2010s catching up, getting the rug pulled out from under me every 10 years or so like everyone else as wealth inequality reached unbelievable levels. Even $1000 for a testing rig felt out of reach. I should probably start with an open source setup, but last I heard, pretty much all FPGAs had a proprietary layer like GPU drivers on Linux, which was such a huge turnoff that I never bothered proceeding further. If that's changed, I'm all ears!
shrubble 3y ago
Do they give you the tools/software for free, or do you have to buy that separately?
- aseipp 3y ago
  Not for these chips. The Vivado licensing is kinda complex these days because it's basically segregated by the chip series rather than actual software features. But it can basically be summed up as "Free for low/mid-range devices with all features, free for people using Alveo accelerators and specific UltraScale SKUs, and pay us money for anything else."
- xodjmk 3y ago
  If you can afford to buy this chip, you wouldn't be worried about the price of tools. But still the situation is much better now than it was in the past. For medium or smaller devices, Ultrascale or Zynq, everything is free, and you don't even need a license. Just install and go. AMD/Xilinx has moved towards a more standard programming environment, Github, open source embedded Linux, etc. Much less of a headache.

110 points by hasheddan 3y ago

VoxPelli 3y ago

So, will CoreScore get a new leader? https://corescore.store/ https://corescore.store/

sitkack 3y ago
That would have been a great marketing stunt!

guepe 3y ago

I'm close to this (I work in emulation) and that chip IS awesome. It is the first fpga really designed with emulation in focus.

currio 3y ago
Can you please tell us, who don't work in the field, what makes this chip awesome
- Taniwha 3y ago
  This chip is for other chip designers - basically when doing chip design you want to make a product that works first time (or explain to your boss why he should spend hi 6 figures on a spin) - so you test test test ... what this is for is that a chip team will take their verilog design, compile it into luts and load it up here, it will likely run at ~10% of your designed speed - the alternative is compiling your verilog to code and have it run at 0.1% - 100x more testing
adwn 3y ago
> It is the first fpga really designed with emulation in focus. Not really. In each generation of devices, Xilinx had one focused on emulation for while now: huge number of LUTs, huge number of general purpose IOs, relatively few DSP elements, a moderate amount of block RAM. Before this monster, it was the Virtex Ultrascale+ VU19P, and before that, the Virtex Ultrascale XCVU440, and before that, the Virtex 7 XC7V2000T.
jonny_eh 3y ago
What does "emulation in focus" mean?
Lramseyer 3y ago
Since so many people are asking what "emulation" is, I'm going to respond to the parent comment instead: "Emulation" refers to emulation of chip designs. When a chip has billions of transistors that are all connected to each other to perform higher level functions, you need to test out designs in order to make sure those higher level functions actually do what you expect them to. Most modern chip designs (at least the digital portions of them) are designed using what's called a Hardware Description Language or "HDL" such as System Verilog or VHDL. It's somewhat similar to traditional programming, except threads are nonexistent, so it's essentially an unholy bastardization of a markup language and a programming language. But I digress... These functions are then synthesized into their low level building blocks such as buses, gates, and registers, and are placed and laid out on a chip. Going back to the part about billions of transistors; as you might imagine, testing of such designs must be rigorous and thorough. Only problem is that it's really, really computationally intensive. There are 2 ways of doing it: Simulation (CPU Based) and Emulation (FPGA Based) Simulation is slower, but yields more data like waveforms and whatnot (though you can get waveforms with emulation, but there are more limits.) Also, simulation takes less time to compile, since there's no place and route step. I should also point out that there are 4 key simulation levels: Simulation Model (usually compiled C code) RTL Simulation (Functional level simulation) Gate level Simulation (simulating the individual gates) and physical simulation (where the transistors and trace routing are all accounted for.) Each level being roughly an order of magnitude more computationally intensive than the previous. Most time and engineering effort is spent on RTL level simulation, which is what can, and is often emulated on an FPGA, and why this product is so relevant to hardware designers.
- Aromasin 3y ago
  If anyone wants to dive a bit deeper into this, I always like to point towards: https://fpgaemu.readthedocs.io/en/latest/ https://fpgaemu.readthedocs.io/en/latest/ If you're a software engineer interested in the hardware side of things, there's a great article for explaining the difference between the programming methodologies: https://nandland.com/lesson-7-what-every-software-programmer-needs-to-understand-about-hardware-design/ https://nandland.com/lesson-7-what-every-software-programmer... To add some extra context, usually when a hardware designer is testing something on an FPGA they'll be testing just one specific IP core (a reusable unit of logic, cell, or integrated circuit layout design that is the intellectual property of the company). Let say, an Ethernet MAC for example. You don't necessarily need a chip like the one in the article to test that. You basically validate what all the inputs and outputs of said IP are going to be; you know that some signals are going to the PCS/PHY and some to a processing core/memory, and provided everything is done correctly then you should be able to slot the IP into your final chip design and everything works. That's not always the case though, which is why some companies end up have many stepping's (revisions of the semiconductor photomasks used to pattern an integrated cirucit). Many companies, my own included, make a business out of designing and selling these IPs to other companies without ever really knowing what the end customer wants to do with it. We just tell them what signals to put in, and what to expect out. With some of the larger FPGAs, you can connect many multiple IPs together and emulate the whole IC, but it depends on scale. You can easily emulate a whole Intel 4004 chip, but you're not fitting a whole Apple M1 design on a single device. With the chip in the article though, we're a step closer to that. Generally you might have 16+ FPGAs on a single PCB to test that scale of functionality. Even that's not a "true" test of a whole IC though, because of the delay in chip-to-chip communication. You might send your design to the foundry and find you've failed on timing. An Agilex 7 M-Series, one of the larger FPGAs in the Intel portfolio, has 3.9M LEs. This chip has what looks to be 18.5M. It's not a 1:1 comparison because they have different architectures, but you get a rough idea of the jump in scale here. This Versal Premium chip will be a massive boon to the likes of Apple, Tesla, NVIDIA, etcetera, because they can potentially emulate the entire chip function on a single die, meaning less steppings to get production quality silicon.

deleted 3y ago

[deleted]

crote 3y ago

For those wondering what an "Adaptive SoC" is supposed to be: It is essentially an FPGA packed together with some ARM cores and interconnects into a single chip.

gjsman-1000 3y ago

For context, "emulation" here is not referring to emulation for video game systems, but for SoC Designers. It could potentially be used for that though if the cost wasn't likely very prohibitive like most FPGAs (and frankly, the VP1902 price tag is likely to be enormous).

cogman10 3y ago
And to be clear, this is a xilinks product. I didn't realize they were purchased by AMD, but they are a old FPGA manufacturer. This isn't "FPGA in your CPU" sort of thing but rather just a generational improvement on existing products.
- tiffanyg 3y ago
  Yup, here's info through Xilinx website (without some of the confusion possible in the current comparatively early stages after acquisition): https://www.xilinx.com/products/silicon-devices/acap/versal-premium/vp1902.html https://www.xilinx.com/products/silicon-devices/acap/versal-... Seems there's still a relative dearth of 3rd party articles, but probably will see at least some more fairly quickly (w/ lifting of embargo etc.).
- iamflimflam1 3y ago
  I did my final year project using a Xilinx FPGA back around 1992. We put some image processing algorithms for fingerprint processing onto it for adaptive thresholding and line thinning. There was a lecturer who was very into hardware software co-design but had got quite disillusioned with it as general purpose CPUs just kept getting faster and faster.
  - photonbeam 3y ago
    Good news then, growth in speed for single threaded has been slowing

kcmastrpc 3y ago

So is this a successor to the DE-10 Nano (the board the MiSTERFPGA project is based on)? (after looking at corescore probably not, as it'd be way too expensive. that being said, the DE-10 Nano is getting old, are there any potential successors coming)?

Foobar8568 3y ago
DE-10 nano is an Intel (Altera) board based on a Cyclone V, I don't think there has been any mindful updates in this price range at Intel.
asguy 3y ago
There are many already available, e.g. ZedBoard, someone just has to do the work to target these other boards and their peripherals/layout.
- MegaDeKay 3y ago
  Nothing is really comparable to the DE-10 Nano's combination of capacity, embedded ARM cores, memory, HDMI scaler, and (most importantly) price. The ZedBoard fails the last test: it is a fair bit more expensive than the Nano. I am keen on the MiSTex project though. The plan is to come up with something that is more flexible than MiSTer to support different targets. So for example, you might be able to target a simpler core to a simpler device and vice versa. https://github.com/MiSTeX-devel https://github.com/MiSTeX-devel https://github.com/enjoy-digital/litex https://github.com/enjoy-digital/litex
  - postalrat 3y ago
    Is there any chance mister could be made to run on pano logic g2 or others? Those are pretty cheap but aren't made any more.
  - asguy 3y ago
    > and (most importantly) price. … OP didn’t mention they were optimizing for price. Some might say it makes sense to optimize for availability, recent updates to hardware software stack, etc.

jhallenworld 3y ago

https://www.theregister.com/2023/06/27/amd_versal_fpga_emulation/ https://www.theregister.com/2023/06/27/amd_versal_fpga_emula... 77 mm x 77 mm package (a bit larger than my old Pentium Pro).. I'm amazed they have any yield for a chip this large at 7 nm. 18 M LEs. 6864 DSPs. 6865 balls. How long does place and route take? $57K for the smaller VP1802.. https://www.digikey.com/en/products/detail/xilinx-inc/XCVP1802-2MSELSVC4072/18627087?utm_source=findchips&utm_medium=aggregator&WT.z_cid=ref_findchips_standard&utm_campaign=buynow https://www.digikey.com/en/products/detail/xilinx-inc/XCVP18...

pclmulqdq 3y ago
The last generation was pushing 12 hours on some of my computers. I assume that if you pay for a top-of-the-line server, you can get one of these done in 4-6 hours or so.
- aseipp 3y ago
  UltraScale+ you mean? Well, the real question is P&R time at some utilization, right? We were easily doing 14hr P&R times on fairly utilized US+ chips like, 5+ years ago. We probably could have improved this in a number of ways, though. I'd honestly think that if you just want to throw money at it, those absurdly-overclocked gamer rigs that can hit sustained +5GHz boosting on just a few cores would be better if you want the fastest P&R times? Cloud servers will probably have more RAM and memory bandwidth but you can shove 128GB of RAM in the 13900K, memory requirements are relatively easy to meet IMO. Synthesis can definitely scale with some more cores in Vivado (OOC synth) but P&R never seemed to scale beyond what you can just get in a desktop. YMMV I guess.
  - pclmulqdq 3y ago
    Yeah, I meant Virtex UltraScale+ parts. I hear that there is a small cottage industry of people overclocking Threadripper workstations for FPGA synthesis, because the memory bandwidth is actually the primary limiting factor (and the Threadrippers have the same kind of turbo capability as the gaming rigs). I assume that the "x3D" chips help a lot, but I don't know.

monocasa 3y ago

So question: my understanding was th atat one point the cadence hardware emulators weren't FPGA based at their core, but instead custom chips with a sea of little one bit processors that only knew about logic ops (with some FPGAs for interchip routing). Is Cadence using FPGAs for logic now too?

wmf 3y ago
It looks like they have two versions: "Palladium Z2 emulation based on a new custom emulation processor offers fastest, most predictable compiles and most comprehensive pre-silicon hardware debug capabilities Protium X2 prototyping based on latest Xilinx UltraScale+ VU19P FPGAs offers highest performance and fastest bring-up times for pre-silicon software validation of billion-gate designs" https://www.cadence.com/en_US/home/company/newsroom/press-releases/pr/2021/cadence-unveils-next-generation-palladium-z2-and-protium-x2-syst.html https://www.cadence.com/en_US/home/company/newsroom/press-re...
throwaway280382 3y ago
Yes. Cadence now has two products. One is custom chip based emulator. Another is FPGA based. I worked on the first version of FPGA based emulator.

zackmorris 3y ago

Finally! I've waited 25 years for something like this, which totally derailed the career I had envisioned for myself. I might even lose the option of making fun of all new chips for providing marginal performance increases for exponentially growing complexity, and have to find a new shtick. A few predictions/concerns: * I can't find a price, so I'm predicting that it will be over $1,000 which will prevent it from going mainstream (and also be ~10 times more expensive than it should be). * There will be poison pill(s). Maybe flash memory that can only be written 1000 times, preventing its use for evolutionary hardware and genetic algorithms. Maybe the place-and-route software won't be good enough to prevent short circuits, so certain configurations will burn up. Maybe some aspect of the software will be proprietary and/or encumbered by patents, preventing hobbyists from thinking outside the box and "getting real work done". * Any dedicated hardware like memories, ALUs, etc may be misaligned for various use-cases. I just want an array of RISC-V, Arm, DEC Alpha, PowerPC 601/603, something like that, starting with 2 and topping 100 or 1000 cores eventually. So where I'll need memories near CPUs, something in the FPGA will lack the interconnect to allow that. I hope I'm wrong about any or all of these. Price I can live with, as long as economies of scale or competition kick in and eventually deliver something under $1,000. The rest of it.. eh, I'm not holding my breath. I've been underwhelmed by all previous FPGAs, but maybe they didn't count. Maybe this is something new that finally manifests the original vision of what FPGAs could be.

adwn 3y ago
> I can't find a price, so I'm predicting that it will be over $1,000 Try 50x to 100x that at quantity=1. This is not a hobbyist device: this FPGA is the largest you can get on, and it's tailored to the needs of companies that spend 7-9 figures on the verification and validation of their ASIC projects. > Maybe this is something new that finally manifests the original vision of what FPGAs could be. Even small to mid-sized modern FPGAs have far surpassed the "original vision of what FPGAs could be".
- zackmorris 3y ago
  You're right, and in fairness I haven't used an FPGA or VHDL since the 90s. I spent the 2000s in destitution and the 2010s catching up, getting the rug pulled out from under me every 10 years or so like everyone else as wealth inequality reached unbelievable levels. Even $1000 for a testing rig felt out of reach. I should probably start with an open source setup, but last I heard, pretty much all FPGAs had a proprietary layer like GPU drivers on Linux, which was such a huge turnoff that I never bothered proceeding further. If that's changed, I'm all ears!

shrubble 3y ago

Do they give you the tools/software for free, or do you have to buy that separately?

aseipp 3y ago
Not for these chips. The Vivado licensing is kinda complex these days because it's basically segregated by the chip series rather than actual software features. But it can basically be summed up as "Free for low/mid-range devices with all features, free for people using Alveo accelerators and specific UltraScale SKUs, and pay us money for anything else."
xodjmk 3y ago
If you can afford to buy this chip, you wouldn't be worried about the price of tools. But still the situation is much better now than it was in the past. For medium or smaller devices, Ultrascale or Zynq, everything is free, and you don't even need a license. Just install and go. AMD/Xilinx has moved towards a more standard programming environment, Github, open source embedded Linux, etc. Much less of a headache.