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Pardon my ignorance on this subject, but at 3 nm, don’t you get into some weird quantum artifacts because the layers are so stupidly close? Curious how that is

Pardon my ignorance on this subject, but at 3 nm, don’t you get into some weird quantum artifacts because the layers are so stupidly close? Curious how that is addressed?

coolspot 4y ago
Not “layers”, but “features”. 3nm is basically a pixel size for chip schematics, it doesn’t mean that they draw 1px features with it.
- samstave 4y ago
  This was always my understanding is that the litho(?) mechanism can "print" in 3nm resolution, which allows the overal scaling of all features to be based on this "pixel" resolution. I was dumbfounded when even hearing about 14NM YEARS before it was a thing (I also got to see 64-core concepts at intel in ~1999 or so) 3nm is mind boggling amazing. Whatever happened to "voxels" (before the graphics term, intel was creating "voxels" that were used to use light to transfer vertically between layers... but I stopped following CPU arch years ago.
  - agar 4y ago
    hah, I remember when "submicron technology" was the bleeding edge of chip design. :-) https://cordis.europa.eu/project/id/554 https://cordis.europa.eu/project/id/554
- ajross 4y ago
  It's not even that. Nothing in a modern process node is as small as the node size, and in fact with modern processes it's not even close. I just checked, and per some reference on wikipedia TSMC 3nm's metal pitch is expected to be 24nm (so, ~12nm wide metal "wires" on the lowest level of interconnect are the smallest things you'll see on a picture). What's been happening is that fabs have been exploiting more and more tricks to increase transistor density while still using the larger feature sizes. So flat transistors became finfet's, increasing their gate area and allowing chips to use fewer of them for the same silicon area, etc... So read "3nm" as "a process with the same transistor density as you would expect had some ancestral ~90nm process been shrunk by a factor of 30".
  - dibujante 4y ago
    Thanks, this is a great explanation. It seems like these "nm" indicators are much like measuring a car's power in "horsepower". It is certainly measuring something real but its connection to actual horses has long since atrophied.
whichquestion 4y ago
The "3nm process" has no bearing on the actual size of the gate's or anything like that and is purely a marketing term. https://en.wikipedia.org/wiki/3_nm_process https://en.wikipedia.org/wiki/3_nm_process gives a reasonable summary in its introduction. My remembrance of the specific quantum effects that you're thinking of are from quantum tunneling[1] of electrons. The problem occurs when the gate size gets small enough that electrons can pass through without the transistor being switched on, which starts to happen around 3nm. [1] https://en.wikipedia.org/wiki/Quantum_tunnelling https://en.wikipedia.org/wiki/Quantum_tunnelling
- fulafel 4y ago
  Interesting that in the WP article it says the gap between the name and the feature size is already ~ 1 order of magnitude: > a 3 nm node is expected to have a contacted gate pitch of 48 nanometers and a tightest metal pitch of 24 nanometers
  - kayson 4y ago
    The name used to correspond to the minimum gate length down to ~14nm. But the smallest feature size in 3nm (i.e. minimum gate length) is certainly much smaller than 24nm.
    - AnimalMuppet 4y ago
      OK, so in "3nm", what is the minimum gate length? And, how many silicon atoms is that?
      - kayson 4y ago
        I couldn't find the information readily available online so I'm not sure I can answer that (all of this stuff is under NDA). But even then, I could only tell you the "drawn" dimension, which is what gets shown on the screen. There are a lot of digital and physical processing steps that change the actual dimensions. Once something is manufactured inevitably one of the IC teardown companies will do a cross section and publish all of this information.
judge2020 4y ago
Note that 3nm and the rest of the process names in the past decade don't actually measure the size of the transistor - it's all marketing[0], and is why Intel is dropping the "nm" naming in favor of "Intel 7, Intel 4, Intel 3, Intel 20A, Intel 18A"[1]. However, maybe someone can link to resources that explain the potential [quantum] hurdles they have to overcome as they've increased density and performance. 0: https://www.pcgamesn.com/amd/tsmc-7nm-5nm-and-3nm-are-just-numbers https://www.pcgamesn.com/amd/tsmc-7nm-5nm-and-3nm-are-just-n... 1: https://www.anandtech.com/show/16823/intel-accelerated-offensive-process-roadmap-updates-to-10nm-7nm-4nm-3nm-20a-18a-packaging-foundry-emib-foveros https://www.anandtech.com/show/16823/intel-accelerated-offen...
- api 4y ago
  They really should just do transistors/mm^2 or transistors/mm^2/watt or something.
  - __alexs 4y ago
    The problem with that measurement is that you get extremely different numbers depending on what you're making. e.g. the density of memory is massively different to the density of logic.
    - farisjarrah 4y ago
      I don't think that's necessarily problematic anymore then measuring fluid viscosity is problematic. Once someone start's getting into debates over the size of transistors on microprocessors then you are already getting pretty wonky and are going to need some science to describe things anyways.
    - bryanlarsen 4y ago
      So you pick something relatively standard (like an SRAM cell), and you use that. There was a concerted effort some time back to formalize a standard measurement of process density using something like "million transistors per square centimetre" by a standards organization. (IEEE?) It wasn't a perfect measurement but it was a lot better than width. It failed so completely that I can't even Google it any more. The awkward name probably didn't help. edit: it's "MT/mm2". Some people actually use it, but more in the informal sense that has the problem you espoused rather than the formalized one, which I still can't find.
bell-cot 4y ago
Yes...but various scaling issues & quantum weirdness & a load of other miseries were ramping up (with each shrink) long, long before 3nm. That's part of why the auto industry can't "just build a fab" for the ~30x larger feature size that their chips need.
- jrockway 4y ago
  I don't think that's what's stopping them building factories for outdated processes, rather it's "after you clear the backlog, there will be no high-margin items to produce". So everyone is just waiting instead. You could make a microcontroller on a 3nm node if you wanted to, but first you'd have to design a new core, and then tell people to pay $100 per chip instead of $0.01. TL;DR: the chip shortage is an economics problem, not a physics problem.
  - bell-cot 4y ago
    Accounts vary, but the chip shortage looks like it will end up costing the auto industry ~~$10 billion in profits. If any major automaker could "just build a fab" - in the sense of "the physics & engineering of ~90nm chip manufacture are pretty simple & cheap, so $250M and 6 months will get us a good-enough fab", then at least one automaker (or A-list supplier) would have done so. If a new fab paid for itself 10X or more before the backlog cleared - no sane CFO would much care whether it was worth keeping open after that. (Edit: Yes, trying to read things in a different way - "weird quantum artefacts" at 3nm have nothing whatever to do with the automakers' problems.) (Edit2: Here is the point which I was originally trying to make: "Chip manufacturing, even at 3nm x ~30 = ~90nm, is still extremely difficult. That fact is a big part of why the automakers did not attempt chip manufacturing, even at ~90nm.")
    - jrockway 4y ago
      Well, I don't think the logistics of 90nm chip manufacture are simple or cheap. It's still pretty high tech stuff, people aren't doing it in their garage. I don't know why automakers didn't engage their partners here to expand manufacturing. I am sure they asked, and the companies that can build 90nm fabs decided not to. Maybe it doesn't make sense after the backlog is cleared, maybe they like the higher prices? And if a car company wanted to start manufacturing chips themselves, they'd have to hire engineers, license patents, work out bugs, etc. and the risk is that the shortage is completely gone after you do all of that. (And, all this during a pandemic. If they wanted to use wood to build the physical building containing the fab, there was a shortage of that. So, a lot of problems to solve, and 10 billion dollars starts looking like a small number.)
eterevsky 4y ago
From my understanding, 3 nm refers not to the size of the gates in transistors, but to the resolution at which they are printed. Similarly printing text at 600 dpi doesn't mean that the actual width of the stems in the letters is 1/600 of an inch.
WithinReason 4y ago
You should be reading "3 nm" as "3 nm equivalent". It doesn't mean anything is 3nm, it's just the simplest way of expressing transistor density without making people transition to a different measurement they are not used to. I would personally like Tr/μm², but I'm fine with nm too.
photochemsyn 4y ago
This seems to be a good discussion. QM effects have already affected design decisions in some cases, and are a major factor in the design of the manufacturing process machinery (which uses extreme UV / soft x-ray): https://semiengineering.com/quantum-effects-at-7-5nm/ https://semiengineering.com/quantum-effects-at-7-5nm/ > "Quantum effects typically occur well behind the curtain for most of the chip industry, baked into a set of design rules developed from foundry data that most companies never see. This explains why foundries and manufacturing equipment companies so far are the only ones that have been directly affected, and they have been making adjustments in their processes and products to account for those effects. But as designs shrink to 7/5nm and beyond, quantum effects are emerging as a more widespread and significant problem, and one that ultimately will affect everyone working at those nodes..." and > "“At very small dimensions of the body, the semiconductor band structure gets ‘quantized,’ so instead of a continuous energy spectrum for the carriers, for example, only discrete energy levels are allowed,” Mocuta said. This quantum confinement has several possible consequences. Among them: • A transistor threshold voltage change. • A change in the density of states (DOS), or the number of carriers available for current conduction. • A change in carrier injection velocity."
- DoctorOetker 4y ago
  The most natural evolution forward would seem to be processing with unconventional quantum-effect phenomena, probably operation specific (addition, multiplication, ...). So not quantum computers in the sense of implementing quantum circuits, but rather opportunistic exploitation of quantum effects. These foundries and manufacturing equipment companies would logically sit on their insights as it might turn out to be a slow but steady march towards miniaturized quantum computers eventually. Think of how thick towels started as a manufacturing defect: a machine in a conventional cloth factory had a part break down, and instead of churning out the usual flat cloth it erroneously wasted a loop of yarn at each 'weave' (for lack of better words as I'm not into weaving). Having no immediate solution at hand to recover the yarn from the thick cloth was sold / distributed as scrap. The problem of the machine was identified and fixed. The users of the cheap scrap came back for more as they discovered the superior water absorbing qualities... Since the fault was documented they could intentionally reproduce the desired 'faulty' cloth.
bhedgeoser 4y ago
qualcomm ceo said that we can reduce transistor sizes by a factor of 1000 before we start seeing issues caused by quantum entanglement.
- rowanG077 4y ago
  That seems a bit far fetched. TSMC N3 has 314.73 MTr/mm2. Just making a quick back of the envelope calculation: 314.73 MTr/mm2 is 3177.3266 nm^2 per transistor. That includes interconnect. Making it 1000x smaller would make a single transistor 3nm^2 including interconnect. I would most definitely expect quantum effects at that level.
  - DoctorOetker 4y ago
    I read the parent comment as citing the claim that quantum entanglement would explicitly manifest.
  - bhedgeoser 4y ago
    Well that's what he said, and I'll believe him over an internet rando any day of the week.
    - ksec 4y ago
      Any links as to when he said it? A quick Google search didn't return any results. Or did you mix up Cristiano Amon with Jim Keller who said something similar?
      - bhedgeoser 4y ago
        In a podcast, couple years ago, can't find the source.
        ksec 4y ago
        If it was a Podcast [1] then it was Jim Keller. And if it was couple of years ago than the CEO of Qualcomm would be Steve Mollenkopf, not Cristiano Amon. And Steve Mollenkopf isn't an engineer so he is highly unlikely to ever say anything like that. [1] https://www.youtube.com/watch?v=Nb2tebYAaOA https://www.youtube.com/watch?v=Nb2tebYAaOA
nl 4y ago
Firstly I'd note that some commentators are saying this number (3nm) is a meaningless marketing term. That's not correct. 3nm means the smallest feature - eg, the width on a channel[1] not the size of a transistor. There are quantum effects at this level (and indeed parger), and one of the big challenges with process design is minimusing them. See [2] for an overview. [1] https://www.electropages.com/blog/2022/05/samsungs-3nm-technology-what-do-we-know https://www.electropages.com/blog/2022/05/samsungs-3nm-techn... [2] https://semiengineering.com/quantum-effects-at-7-5nm/ https://semiengineering.com/quantum-effects-at-7-5nm/ [1] https://www.electropages.com/blog/2022/05/samsungs-3nm-technology-what-do-we-know https://www.electropages.com/blog/2022/05/samsungs-3nm-techn...

Pardon my ignorance on this subject, but at 3 nm, don’t you get into some weird quantum artifacts because the layers are so stupidly close? Curious how that is addressed?

coolspot 4y ago

Not “layers”, but “features”. 3nm is basically a pixel size for chip schematics, it doesn’t mean that they draw 1px features with it.

samstave 4y ago
This was always my understanding is that the litho(?) mechanism can "print" in 3nm resolution, which allows the overal scaling of all features to be based on this "pixel" resolution. I was dumbfounded when even hearing about 14NM YEARS before it was a thing (I also got to see 64-core concepts at intel in ~1999 or so) 3nm is mind boggling amazing. Whatever happened to "voxels" (before the graphics term, intel was creating "voxels" that were used to use light to transfer vertically between layers... but I stopped following CPU arch years ago.
- agar 4y ago
  hah, I remember when "submicron technology" was the bleeding edge of chip design. :-) https://cordis.europa.eu/project/id/554 https://cordis.europa.eu/project/id/554
ajross 4y ago
It's not even that. Nothing in a modern process node is as small as the node size, and in fact with modern processes it's not even close. I just checked, and per some reference on wikipedia TSMC 3nm's metal pitch is expected to be 24nm (so, ~12nm wide metal "wires" on the lowest level of interconnect are the smallest things you'll see on a picture). What's been happening is that fabs have been exploiting more and more tricks to increase transistor density while still using the larger feature sizes. So flat transistors became finfet's, increasing their gate area and allowing chips to use fewer of them for the same silicon area, etc... So read "3nm" as "a process with the same transistor density as you would expect had some ancestral ~90nm process been shrunk by a factor of 30".
- dibujante 4y ago
  Thanks, this is a great explanation. It seems like these "nm" indicators are much like measuring a car's power in "horsepower". It is certainly measuring something real but its connection to actual horses has long since atrophied.

whichquestion 4y ago

The "3nm process" has no bearing on the actual size of the gate's or anything like that and is purely a marketing term. https://en.wikipedia.org/wiki/3_nm_process https://en.wikipedia.org/wiki/3_nm_process gives a reasonable summary in its introduction. My remembrance of the specific quantum effects that you're thinking of are from quantum tunneling[1] of electrons. The problem occurs when the gate size gets small enough that electrons can pass through without the transistor being switched on, which starts to happen around 3nm. [1] https://en.wikipedia.org/wiki/Quantum_tunnelling https://en.wikipedia.org/wiki/Quantum_tunnelling

fulafel 4y ago
Interesting that in the WP article it says the gap between the name and the feature size is already ~ 1 order of magnitude: > a 3 nm node is expected to have a contacted gate pitch of 48 nanometers and a tightest metal pitch of 24 nanometers
- kayson 4y ago
  The name used to correspond to the minimum gate length down to ~14nm. But the smallest feature size in 3nm (i.e. minimum gate length) is certainly much smaller than 24nm.
  - AnimalMuppet 4y ago
    OK, so in "3nm", what is the minimum gate length? And, how many silicon atoms is that?
    - kayson 4y ago
      I couldn't find the information readily available online so I'm not sure I can answer that (all of this stuff is under NDA). But even then, I could only tell you the "drawn" dimension, which is what gets shown on the screen. There are a lot of digital and physical processing steps that change the actual dimensions. Once something is manufactured inevitably one of the IC teardown companies will do a cross section and publish all of this information.

judge2020 4y ago

Note that 3nm and the rest of the process names in the past decade don't actually measure the size of the transistor - it's all marketing[0], and is why Intel is dropping the "nm" naming in favor of "Intel 7, Intel 4, Intel 3, Intel 20A, Intel 18A"[1]. However, maybe someone can link to resources that explain the potential [quantum] hurdles they have to overcome as they've increased density and performance. 0: https://www.pcgamesn.com/amd/tsmc-7nm-5nm-and-3nm-are-just-numbers https://www.pcgamesn.com/amd/tsmc-7nm-5nm-and-3nm-are-just-n... 1: https://www.anandtech.com/show/16823/intel-accelerated-offensive-process-roadmap-updates-to-10nm-7nm-4nm-3nm-20a-18a-packaging-foundry-emib-foveros https://www.anandtech.com/show/16823/intel-accelerated-offen...

api 4y ago
They really should just do transistors/mm^2 or transistors/mm^2/watt or something.
- __alexs 4y ago
  The problem with that measurement is that you get extremely different numbers depending on what you're making. e.g. the density of memory is massively different to the density of logic.
  - farisjarrah 4y ago
    I don't think that's necessarily problematic anymore then measuring fluid viscosity is problematic. Once someone start's getting into debates over the size of transistors on microprocessors then you are already getting pretty wonky and are going to need some science to describe things anyways.
  - bryanlarsen 4y ago
    So you pick something relatively standard (like an SRAM cell), and you use that. There was a concerted effort some time back to formalize a standard measurement of process density using something like "million transistors per square centimetre" by a standards organization. (IEEE?) It wasn't a perfect measurement but it was a lot better than width. It failed so completely that I can't even Google it any more. The awkward name probably didn't help. edit: it's "MT/mm2". Some people actually use it, but more in the informal sense that has the problem you espoused rather than the formalized one, which I still can't find.

bell-cot 4y ago

Yes...but various scaling issues & quantum weirdness & a load of other miseries were ramping up (with each shrink) long, long before 3nm. That's part of why the auto industry can't "just build a fab" for the ~30x larger feature size that their chips need.

jrockway 4y ago
I don't think that's what's stopping them building factories for outdated processes, rather it's "after you clear the backlog, there will be no high-margin items to produce". So everyone is just waiting instead. You could make a microcontroller on a 3nm node if you wanted to, but first you'd have to design a new core, and then tell people to pay $100 per chip instead of $0.01. TL;DR: the chip shortage is an economics problem, not a physics problem.
- bell-cot 4y ago
  Accounts vary, but the chip shortage looks like it will end up costing the auto industry ~~$10 billion in profits. If any major automaker could "just build a fab" - in the sense of "the physics & engineering of ~90nm chip manufacture are pretty simple & cheap, so $250M and 6 months will get us a good-enough fab", then at least one automaker (or A-list supplier) would have done so. If a new fab paid for itself 10X or more before the backlog cleared - no sane CFO would much care whether it was worth keeping open after that. (Edit: Yes, trying to read things in a different way - "weird quantum artefacts" at 3nm have nothing whatever to do with the automakers' problems.) (Edit2: Here is the point which I was originally trying to make: "Chip manufacturing, even at 3nm x ~30 = ~90nm, is still extremely difficult. That fact is a big part of why the automakers did not attempt chip manufacturing, even at ~90nm.")
  - jrockway 4y ago
    Well, I don't think the logistics of 90nm chip manufacture are simple or cheap. It's still pretty high tech stuff, people aren't doing it in their garage. I don't know why automakers didn't engage their partners here to expand manufacturing. I am sure they asked, and the companies that can build 90nm fabs decided not to. Maybe it doesn't make sense after the backlog is cleared, maybe they like the higher prices? And if a car company wanted to start manufacturing chips themselves, they'd have to hire engineers, license patents, work out bugs, etc. and the risk is that the shortage is completely gone after you do all of that. (And, all this during a pandemic. If they wanted to use wood to build the physical building containing the fab, there was a shortage of that. So, a lot of problems to solve, and 10 billion dollars starts looking like a small number.)

eterevsky 4y ago

From my understanding, 3 nm refers not to the size of the gates in transistors, but to the resolution at which they are printed. Similarly printing text at 600 dpi doesn't mean that the actual width of the stems in the letters is 1/600 of an inch.

WithinReason 4y ago

You should be reading "3 nm" as "3 nm equivalent". It doesn't mean anything is 3nm, it's just the simplest way of expressing transistor density without making people transition to a different measurement they are not used to. I would personally like Tr/μm², but I'm fine with nm too.

photochemsyn 4y ago

This seems to be a good discussion. QM effects have already affected design decisions in some cases, and are a major factor in the design of the manufacturing process machinery (which uses extreme UV / soft x-ray): https://semiengineering.com/quantum-effects-at-7-5nm/ https://semiengineering.com/quantum-effects-at-7-5nm/ > "Quantum effects typically occur well behind the curtain for most of the chip industry, baked into a set of design rules developed from foundry data that most companies never see. This explains why foundries and manufacturing equipment companies so far are the only ones that have been directly affected, and they have been making adjustments in their processes and products to account for those effects. But as designs shrink to 7/5nm and beyond, quantum effects are emerging as a more widespread and significant problem, and one that ultimately will affect everyone working at those nodes..." and > "“At very small dimensions of the body, the semiconductor band structure gets ‘quantized,’ so instead of a continuous energy spectrum for the carriers, for example, only discrete energy levels are allowed,” Mocuta said. This quantum confinement has several possible consequences. Among them: • A transistor threshold voltage change. • A change in the density of states (DOS), or the number of carriers available for current conduction. • A change in carrier injection velocity."

DoctorOetker 4y ago
The most natural evolution forward would seem to be processing with unconventional quantum-effect phenomena, probably operation specific (addition, multiplication, ...). So not quantum computers in the sense of implementing quantum circuits, but rather opportunistic exploitation of quantum effects. These foundries and manufacturing equipment companies would logically sit on their insights as it might turn out to be a slow but steady march towards miniaturized quantum computers eventually. Think of how thick towels started as a manufacturing defect: a machine in a conventional cloth factory had a part break down, and instead of churning out the usual flat cloth it erroneously wasted a loop of yarn at each 'weave' (for lack of better words as I'm not into weaving). Having no immediate solution at hand to recover the yarn from the thick cloth was sold / distributed as scrap. The problem of the machine was identified and fixed. The users of the cheap scrap came back for more as they discovered the superior water absorbing qualities... Since the fault was documented they could intentionally reproduce the desired 'faulty' cloth.

bhedgeoser 4y ago

qualcomm ceo said that we can reduce transistor sizes by a factor of 1000 before we start seeing issues caused by quantum entanglement.

rowanG077 4y ago
That seems a bit far fetched. TSMC N3 has 314.73 MTr/mm2. Just making a quick back of the envelope calculation: 314.73 MTr/mm2 is 3177.3266 nm^2 per transistor. That includes interconnect. Making it 1000x smaller would make a single transistor 3nm^2 including interconnect. I would most definitely expect quantum effects at that level.
- DoctorOetker 4y ago
  I read the parent comment as citing the claim that quantum entanglement would explicitly manifest.
- bhedgeoser 4y ago
  Well that's what he said, and I'll believe him over an internet rando any day of the week.
  - ksec 4y ago
    Any links as to when he said it? A quick Google search didn't return any results. Or did you mix up Cristiano Amon with Jim Keller who said something similar?
    - bhedgeoser 4y ago
      In a podcast, couple years ago, can't find the source.
      - ksec 4y ago
        If it was a Podcast [1] then it was Jim Keller. And if it was couple of years ago than the CEO of Qualcomm would be Steve Mollenkopf, not Cristiano Amon. And Steve Mollenkopf isn't an engineer so he is highly unlikely to ever say anything like that. [1] https://www.youtube.com/watch?v=Nb2tebYAaOA https://www.youtube.com/watch?v=Nb2tebYAaOA

nl 4y ago

Firstly I'd note that some commentators are saying this number (3nm) is a meaningless marketing term. That's not correct. 3nm means the smallest feature - eg, the width on a channel[1] not the size of a transistor. There are quantum effects at this level (and indeed parger), and one of the big challenges with process design is minimusing them. See [2] for an overview. [1] https://www.electropages.com/blog/2022/05/samsungs-3nm-technology-what-do-we-know https://www.electropages.com/blog/2022/05/samsungs-3nm-techn... [2] https://semiengineering.com/quantum-effects-at-7-5nm/ https://semiengineering.com/quantum-effects-at-7-5nm/ [1] https://www.electropages.com/blog/2022/05/samsungs-3nm-technology-what-do-we-know https://www.electropages.com/blog/2022/05/samsungs-3nm-techn...