6 ms·
Computers Without Clocks – Ivan Sutherland (2002) [pdf]
- rathel 6y agoThe whole digital ASIC synthesis flow revolves around timing closure i.e. satisfying setup and hold at max possible clock speed. I guess we may even have to invent a new HDL to pursue asynchronous paradigm efficiently.
- gradschool 6y agoTrue, but inventing a new language for asynchronous hardware wouldn't be as big of a job as reinventing an industry standard like VHDL. Something like a small lightweight concurrent process description formalism with a Petri net based operational semantics would do nicely, and such things have been well understood for decades. The hard part is for it to gain traction.
- rathel 6y agoAs Moore's law slows down, this time for real, there have been a few unorthodox ideas lately. 3DIC, or Cerebras' whole-wafer CPU. This looks like a thing worthy pursuing. With free money and big corps racing for a market first (disruptors trying not to be disrupted), who knows. I wonder how much in terms of power-performance-area can be gained from going asynchronous.
- gradschool 6y agoThere have been many quantitative studies presented over the years at the IEEE Async conferences [1]. The best use cases until now have been niche applications calling for ultra-low power where performance isn't too critical. [1] https://asyncsymposium.org/ https://asyncsymposium.org/
- Junk_Collector 6y agoLadder logic already exists and was designed for documenting and programming asynchronous clock-less computers. The problem is that it's like programming C++ in the early 90's where every hardware vendor sells you their own proprietary implementation.
- orbifold 6y agoThis has been tried before: https://academic.oup.com/comjnl/article-abstract/45/1/12/338521?redirectedFrom=fulltext https://academic.oup.com/comjnl/article-abstract/45/1/12/338...
- marcosdumay 6y agoEven performance specification gets harder. How does one benchmark the latest AMD and Intel processors if performance is different for each unit (and completely changes for each workload)? Asynchronous circuits are full of promises (the largest ones on the low power segment), the reason they are not standard is because the are hard.
- gradschool 6y agoAren't we heading for the same problem the way things are going with dynamic frequency scaling in AMD and Intel processors? How do you predict when a particular workload running a little hotter than anticipated will make it kick in? If the answer is to benchmark them at the factory under carefully controlled conditions and reject those that don't fall within a narrow range, then what's the difference?
- marcosdumay 6y agoIt's similar. The difference is that there are way more dimensions in asynchronous processors. Anyway, when I was studying the subject, the one problem people wrote about was testing. I think the GP's problem and the one I pointed can only get some attention after tests get reasonably solved, and they both may be easier than they look like.
- dnautics 6y ago> the reason they are not standard is because the are hard. With your first sentence, I was really hoping that the punchline was going to be "because they are hard to market"... Not only because superficially I'm a cynic, but also because it implies that there's some hope since the MHz/GHz wars are probably at their end or near their end.
- marcosdumay 6y agoThey are hard at every dimension. To market included. But it doesn't get much attention right now because people are still stuck at the designing, building and testing stages.
- ekiwi 6y agoYou also have to keep in mind that modern flows can already automatically place more area/power efficient but slower transistors on the non-critical paths. Thus signals can get balanced and the wasted area/performance is not as big as one might think.
- EdwardCoffin 6y agoArchive.org has their old website, fleet.cs.berkeley.edu, which includes various publication and slides from talks [1] [1] https://web.archive.org/web/20090423133512/http://fleet.cs.berkeley.edu/ https://web.archive.org/web/20090423133512/http://fleet.cs.b...
- jacquesm 6y agoAh, one of my hobby horses. I'd love for this to take off but so far I have not seen anything that convinced me that it will. I have a proof-of-concept of 'life' in clockless form, which was quite a bit of a headache, and since life is theoretically Turing complete that generalizes to the possibility of making clockless computers at scale. The one nasty little detail is that the computer implemented on the life substrate would have a clock simulated in life... Pretty hard to get around that limitation.
- gradschool 6y agoMy favorite subject too. Do you have a writeup posted anywhere? What delay model did you assume (e.g., SI, DI, QDI, burst mode, something else)? FWIW, the Amulet processor from the Manchester group and a prototype from Martin's group at Caltech have demonstrated that asynchronous general purpose processors are possible.
- jacquesm 6y agoI don't remember ever doing a proper write up of that project, I was hip deep into all kinds of esoteric computing a few years ago (which started with brainfuck and ended with computing fabrics). Fascinating stuff. I was not aware of the Amulet processor, I will definitely look into that, thank you very much for the pointer. edit: http://apt.cs.manchester.ac.uk/projects/processors/amulet/AMULET3i.php http://apt.cs.manchester.ac.uk/projects/processors/amulet/AM... They apparently almost got it deployed commercially, which would have been fairly big news.
- sitkack 6y agoI think there are more clockless designs out there but they are "secret sauce". From a previous discussion on clockless silicon https://news.ycombinator.com/item?id=18146750 https://news.ycombinator.com/item?id=18146750 The Intel exec who left to form a clockless startup looks like they are doing AI accelerators with 1000x less power https://etacompute.com/ https://etacompute.com/
- tgvaughan 6y agoWow. Somehow this feels like an even more extreme version of Carl Hewitt's actor model in which individual actors themselves involve asynchronous components.
- chaganated 6y agoI believe Chuck Moore took a stab at this with "Green Arrays" http://www.greenarraychips.com/ http://www.greenarraychips.com/
- frompdx 6y agoI saw the title and was going to comment about the same thing. My understanding is the GA144 is clockless. From the product literature the advantage is reduced power consumption. It is also a Forth machine. I've wanted to get one of these for a while but the eval board price is a little steep for someone who just wants to tinker with it. The chip individually is not terribly expensive. At one point there was a budget version available for around $20 but these are no longer available.
- tikhonj 6y agoI worked on a research project using these—the design is totally wild, and not just because they don't have clocks. I remember talking to one of the other people at the company, and he had a debugging story that—if I'm recalling correctly—came down to one core seeing the output of another core part way through the register being updated. Cores communicate by linking the top registers of their stacks against the top register of neighboring cores and, since there's no system-wide clock, two cores can run slightly out of step with one another. That must not have been easy to diagnose! I suppose that's the trade-off with not having clocks, although I don't really know enough about computer architecture to judge.
- hinkley 6y agoI wonder if it makes sense to have two identical cores trying to talk to each other without a clock to sync them. If they were more big.LITTLE style you might not fool yourself into thinking you can count on any congruity between runs or over time. External systems have clocks build into their communications protocols. Maybe the cores are just islands unto themselves.
- bullen 6y agoI made a completely async. HTTP app. server and then added a distibuted async. JSON database on top: https://github.com/tinspin/rupy https://github.com/tinspin/rupy The problem with async. is that once you add one thing as async., you need to change everything to be async. for it to work well! That said time is the hardest thing that humans have to deal with, we simply are not built to understand it.
- sitkack 6y agoI got to chat with Ivan after he gave a talk about Fleet at the University of Washington a bunch of years ago. He strikes me as down to earth and intellectually honest in ways that most people are not. A similar architecture at the software level is to have thread per core and queues to move data between threads as in Seastar, Glommio, etc. https://github.com/scylladb/seastar/blob/master/doc/tutorial.md https://github.com/scylladb/seastar/blob/master/doc/tutorial... https://www.datadoghq.com/blog/engineering/introducing-glommio/ https://www.datadoghq.com/blog/engineering/introducing-glomm...
- whoisthemachine 6y agoThis article takes me back to my college days ca. 2009, my senior design project was asynchronous cryptography circuits... I read this article and a few research papers more than a few times before I gained an entry level understanding of asynchronous circuits. Unfortunately the entire concept was very difficult for even senior computer engineering students to wrap their heads around when they had just been studying clocked circuits in-depth. Understanding the mueller-c element [0] in particular caused me significant difficulties. Understanding the concept from a high-level isn't too bad however. As the article covers, if you visualize each piece of information moving along the pipeline as a hand-off, like a chain of people passing balls to each other, with the rule that they can't pass a new ball until they've passed the previous ball, you have a rough idea of how asynchronous processing circuits work. What's funny is that a natural "clock" begins to take shape at that point, although it's determined by the slowest component in your pipeline, rather than by an oscillator. The ball diagrams from the Rx libraries are actually also good visualizations for asynchronous circuits [1]. Those were some rough months attempting to achieve our advisor's goals, clearly the trauma still hasn't left me. [0] https://en.wikipedia.org/wiki/C-element https://en.wikipedia.org/wiki/C-element [1] Example Ball Diagram from the Rx libraries: http://reactivex.io/documentation/operators/map.html http://reactivex.io/documentation/operators/map.html