ekiwi

9 ms·

1.
by ekiwi 3y ago
One solution is e-bikes which are getting better every year and will allow you to go quite far without breaking a sweat.
2.
by ekiwi 3y ago
The 32-bit aligned instruction assumption is probably baked into their low-level caches, branch predictors etc. That might mean much more significant work for switching to 16-bit instructions than they are willing to do.
3.
by ekiwi 4y ago
They verified the protocol, not the actual implementation: https://github.com/rosenpass/rosenpass#security-analysis This is still a pretty neat result! End-to-end proofs from high level protocol to low level implementa
4.
by ekiwi 5y ago
My biggest question after looking at the readme: What happens if your computer crashes while dura is making a commit? Can it corrupt your local git repository? From my own experience, git is not crash safe, i.e., it can leave the .git direc
5.
by ekiwi 5y ago
> nuclear waste is not waste There is a lot more to nuclear waste than just the fuel rods. Lots of materials that are either used by workers at the plant or part of the plant become radio active and can no longer go to a regular landfill
6.
by ekiwi 5y ago
> if the two of them don't decide to add their own proprietary "extensions" to the language. icc has always had its own dialect of C++, which in practice means that there is "C++" code that only compiles on icc b
7.
by ekiwi 5y ago
> At best you can do the same with one reduced canonical simplified verilog source-to-source translation. Parsing Verilog and generating valid Verilog is fairly difficult. If you want to stay with Verilog, the most realistic alternative
8.
by ekiwi 5y ago
> Access to any global variable should always occur direct from memory. What if your function takes a pointer that might be pointing to a global variable? Does that mean that all accesses through a pointer are now excempt from optimizati
9.
by ekiwi 5y ago
> Chisel is therefore it's "synthesizable subset". Chisel is not synthesizing Scala. It is just a library implemented in Scala that allows you to create a data structure that describes a circuit. Something like: circui
10.
by ekiwi 5y ago
Chisel imho solves the "synthesizable subset" problem quite elegantly: All Chisel constructs are simple, synthesizable circuit elements and boolean functions (+ functions on fixed size integers that can be converted into boolean f
11.
by ekiwi 5y ago
Chisel is not HLS. It is a Scala library that lets you generate circuits on an RTL abstraction level. That means that you explicitly define every state element like registers and memories. But you can generate N registers inside a loop (or
12.
by ekiwi 5y ago
Did you see the work being done on CIRCT? https://github.com/llvm/circt I remember one of the reasons you did not want to use firrtl was that its compiler is implemented in Scala and thus hard to integrate into other p
13.
by ekiwi 5y ago
It was in fact the EdgeTPU (which is different from the TPU used in data centers). The talk from a google engineer can be found on youtube: https://www.youtube.com/watch?v=x85342Cny8c Please note that they were using a vers
14.
by ekiwi 5y ago
I think the hardest problem is contributing changes back upstream. With hardware, people are a lot more paranoid about introducing new bugs and I feel like that sometimes makes collaboration a lot more difficult.
15.
by ekiwi 5y ago
Sounds like nmigen might be a good open source successor to the project that you describe: https://github.com/nmigen/nmigen There are lots of open-source (n)migen components available through the litex framework: http
16.
by ekiwi 5y ago
If you hit the Windows key on Gnome 3, you can type the name of a program, file or system setting and it will generally find it.
17.
by ekiwi 6y ago
Glacial was one of the entries for the 2018 RISC-V SoftCPU Contest, but I think it wasn't ready by the deadline. If you look at the winners there was another 8-bit CPU with a RISC-V interpreter, SERV, VexRiscv but also Reindeer which s
18.
by ekiwi 6y ago
How do you deal with structured formats, like XML? In JQF you would just write a XML generator (see their examples). If you just use the "sequence of bytes" approach as AFL does, then a lot of your inputs might be immediately reje
19.
by ekiwi 6y ago
If you are interested in fuzzing your Java code, you should also have a look at the JQF project which directly integrates with junit tests: https://github.com/rohanpadhye/JQF
20.
by ekiwi 6y ago
This is the latest paper on BOOM: http://people.eecs.berkeley.edu/~krste/papers/SonicBOOM-CARR... It has some comparisons so you can judge for yourself. Of course, since this is a project driven by only 2-3 grad s
21.
by ekiwi 6y ago
> It used to be you could email a patch to someone and that patch would get reviewed and committed. Yes, but 1990 is also when this study came out: https://ftp.cs.wisc.edu/par-distr-sys/technical_papers/fuzz...
22.
by ekiwi 6y ago
You might be interested in this work which integrates a programmable fabric directly with a MIPS core in order to speed up inner loops: http://brass.cs.berkeley.edu/garp.html
23.
by ekiwi 6y ago
You also have to keep in mind that modern flows can already automatically place more area/power efficient but slower transistors on the non-critical paths. Thus signals can get balanced and the wasted area/performance is not as bi
24.
by ekiwi 6y ago
The problem with delay slots is that their optimal size is somewhat tied to the particular micro-architecture. I.e., different MIPS CPU implementations would have different optimal branch delay slot sizes. This doesn't matter too much
25.
by ekiwi 6y ago
> I thought Berkeley's BOOM is way more advanced implementation of RISCV than VexRiscV and it is written in Chisel3. It is a lot more advanced and thus harder to get started with than VexRiscV. > BOOM does not look like most effe
26.
by ekiwi 6y ago
I think in general Chisel has more people working on it. However, most people using Chisel are targeting ASICs, thus Spinal HDL wins when it comes to supporting features that are important to FPGAs. Chisel also hasn't anything close to
27.
by ekiwi 6y ago
In case you have a FOMU and are interested in exploring Chisel, I recently added a simple Blink example that should help people get started: https://github.com/im-tomu/fomu-workshop/blob/master/chisel&#x2
28.
by ekiwi 6y ago
It seems like the real challenge would not be the translation of individual code snippets to a newer programming language, but more about adapting the code base to a different library eco-system. For example you would have to understand the
29.
by ekiwi 7y ago
If you want to find the source code and some information on how to build and run it, you should check out their new website: https://boom-core.org/
30.
by ekiwi 7y ago
Wouldn't you also need a way of storing information (preferably an unlimited amount of information) for Skylines to be turing complete? How would you implement the tape of the turing machine?

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