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Tin Plasma Extreme Ultraviolet Radiation Makes 5nm Integrated Circuits Possible
- baybal2 7y agoA tidbit, a one of more lunatical proposal for the next gen fab design is to build it around a multimegawatt cyclotron, and have the light source problem "solved for good" The genuine problem with tin plasma laser is its power efficiency. An early adopter runs can bare with 0.02% energy efficiency, but imagine, say, a few 20 line fabs and their power consumption. Another very important advantage of this design would be getting a more stable, easily tunable, and more narrowband light source. Tin plasma has around 1nm deviation in its spectrum, while a cyclotron can get to picometres on an arbitrary wavelength. And with all above, you get a supremely tempting option to try diffractive optics, and do away with all geometry imposes nonsense of EUV reflective optics...
- guepe 7y agoI had a similar idea of using synchrotron to generate very low wavelength light for lithography... I guess costs are an issue!
- baybal2 7y agoThe "lighbulb" in 3400 costs as much as a small research synchrotron already
- epicureanideal 7y agoWhat's 3400?
- baybal2 7y agohttps://www.asml.com/-/media/asml/files/products/twinscan-nxe3400b.pdf https://www.asml.com/-/media/asml/files/products/twinscan-nx...
- robocat 7y ago"User Interface LINUX Architecture The system is delivered with proprietary ASML TWINSCAN software based on the Linux/Voyager operating system. Separate computing hosts are used for data access and scanner control offering the following automation interfaces: SECS, EDI, and EDA."
- madengr 7y agoA 26x33 mm die would yield 86E9 transistor. Pretty impressive.
- eigenloss 7y agoNot a useful comparison. A single neuron is far better networked to its neighbors and far more complex/nonlinear than a transistor. There are already chips out there with 1e11 transistors, but they don't run "ai" even a little bit. Assuming you need something like 1e5 transistors to approximate one neuron, you'd need like 100m^2 of die area and interconnect to actually emulate a brain.
- anticensor 7y agoAnd you would still lag due to speed of light issues.
- Escapado 7y agoIf we get plasma wakefield accelerators working better we could build a table top free electron laser and just go with that!
- the8472 7y agoHigh level descriptions of semiconductor fabrication is what scifi tech porn wants to be. Throwing an accelerator in there doesn't seem out of place. I wouldn't be surprised if they already used them for some other purposes.
- extrapickles 7y agoParticle accelerators are used, though I'm not aware of anyone doing so for production semiconductors. They are used for doping and someone was using one for cleaving solar cells off of a silicon ingot, so there would be no kerf losses.
- MrEldritch 7y agoMy father used to work for Intel, back in the '80s and '90s - he's mentioned this proposal before. Apparently this is not even remotely a new idea, and even back in the late 90s, they were expecting to have to move to this model eventually.
- bprater 7y agoFor the curious: 100,000,000 transistors per square millimeter, from the site.
- overcast 7y agoFor the extra curious, more transistors = more parallelism, bigger cache.
- LegitShady 7y agoIt's even better than that. Smaller transistors require less energy to switch, and also switch faster.
- Symmetry 7y agoThe switching faster bit has only been happening very incrementally with the breakdown of Dennard scaling. Thankfully the less energy bit seems to be part of a more fundamental process than Moore's Law[1] and there are nice, clear, theoretical limits on how power efficient a computation can be which we're nowhere near hitting[2]. [1]https://en.wikipedia.org/wiki/Koomey%27s_law https://en.wikipedia.org/wiki/Koomey%27s_law [2]https://en.wikipedia.org/wiki/Landauer%27s_principle https://en.wikipedia.org/wiki/Landauer%27s_principle
- Causality1 7y agoIntel's been claiming that density for over two years. https://spectrum.ieee.org/nanoclast/semiconductors/processors/intel-now-packs-100-million-transistors-in-each-square-millimeter https://spectrum.ieee.org/nanoclast/semiconductors/processor...
- dmoy 7y agoProcess size isn't uniform between fabs. One fab's 10nm might be roughly the same as another's 7nm or so.
- pflanze 7y ago
- j_coder 7y agoI can imagine on a few decades company's data center on a single square meter chip :)
- mises 7y ago...and the rest of the space being taken by a colossal cooling system.
- olliej 7y agoThat would be colossally inefficient - essentially the size of the chip means that electrons would be taking multiple cycles to get from one side to the other. The solution would be localizing processing into distinct processing units on the one die. At the point you’ve reinvented multiple cores and it starts becoming cost effective to split them into separate chips to improve yields :)
- pixl97 7y agoThat is only on a clock locked chip. There are chips with designs where different parts of a chip where clocks run at different cycles.
- verall 7y agoYea, why even use synchronous clocks? Asynch designs have been around since the 80s /s
- deepnotderp 7y agoMost complex chips today already have multiple clock domains, don't see why that would be a problem.
- olliej 7y agoMost modern chips already use numerous clocks (aside from anything else propagation delays for the clock signal is already a problem). The problem is not simply "because clock cycle" it is "if electron takes Xns to get from one execution unit to the next, then that's Xns of functionally idle time". That at best means additional latency. The more latency involved in computing a result the more predictive logic you need - for dependent operations the latency matters. An asynchronous chip does not avoid that same problems encountered by a multistage pipelined processor, it's purely a different way to manage varying instruction execution times. But this doesn't answer the killer problem of yield. The larger a single chip is the more likely any given chip is to have errors, and therefore the fewer chips you get out of a given wafer after the multiple weeks/months that wafer has been trundling through a fab. Modern chips put a lot of redundancy in to maximize the chance that sufficient parts of a given core survive manufacture to allow a complete chip to function, eg. more fabricated cache and execution units than necessary, at the end of manufacture any components that have errors are in effect lasered out. If at that point any chip doesn't have enough remaining cache/execution units, or an error occurs where it can't be redundant, the entire chip is dead. The larger a given die is the greater the chance that the entire die will be written off. That massive ML chip a few days ago worked by massively over prescribing execution units. I suspect that they end up with much greater lost area of a given wafer than many small chips, which directly contributes to actual cost.
- RcouF1uZ4gsC 7y agoReading this, I realized that I have no ability to differentiate actual in use fab technology from science fiction. What the engineers and scientists do in modern fabs is in my mind more impressive than the entire Apollo program.
- tempsolution 7y agoThere is nothing particularly impressive about the Apollo program, at least not these days. You are essentially comparing today's frontier of High-Tech research with 50 year old "needs to work reliably" technology, which had different requirements even back then.
- lgats 7y agoHumans went to the moon. I'm impressed. Magic box I hold in my hand to communicate near-instantaneously with the other side of the world... somehow less impressive.
- MaysonL 7y ago"Every now and again there is a moment that brings home how strange life in the twenty-first century can be. There I was in Brighton, England, holding a thin slice of glass and metal which was made in South Korea and ran American software, and which could show me the President of America threatening the Supreme Leader of North Korea." John Higgs: Stranger Than We Can Imagine an alternative history of the 20th century, p. 5
- basementcat 7y agoPart of sending humans to the moon included the equipment to talk with them while they were there. EDIT: And bring back live video.
- Fr0styMatt88 7y agoIt's amazing when you remind yourself that your web request is actually causing something physical to happen on the other side of the world. That blows my mind every time I really think about it. It's all so seamless most of the time that it's easy to forget that it's an actual physical process that happens in the real world, with real EM waves travelling through the real physical world.
- pfdietz 7y agoOne of the applications of shear-flow stabilized Z pinches is to generate short wavelength light from xenon plasmas.
- ttul 7y agoThis is why I read HN.
- londons_explore 7y agoWhy are people putting lots of effort into extreme UV generators when we could just use x-rays? We know plenty of ways to generate and focus x-rays...
- robbiep 7y agoJust a guess as I am not in the industry but I would imagine has to do with the photoresists and masks - perhaps we don’t have ones that work with X-ray. Not much good using a wavelength that passes through or is unabsorbed by the resist material!
- Itsdijital 7y agoIIRC we don't even have masks that can really take EUV, the mask is destroyed after each exposure.
- torpfactory 7y agoI think the masks can take it but their is a ton of difficulty in inspecting the masks themselves for defects. IIRC the leading candidate at the time I was in the industry was to actually expose wafers and then scan the wafers for defects which originated on the mask, hoping to not confuse these with other process defects. Not sure how they ended up solving that one.
- deepnotderp 7y agoNot just that but high throughput pellicles (prevents dust from ko-ing you) haven't hit production yet iirc
- jacquesm 7y agoDo multiple exposures and see which defects come up more than once?
- torpfactory 7y ago
- lstodd 7y agoLet's do hard gamma lithography already.
- chc4 7y agoIf you're interested in chip fabrication, I heartily recommend watching https://youtu.be/NGFhc8R_uO4 https://youtu.be/NGFhc8R_uO4 - it goes over the evolution of how they make transistors all the way up to 2009 state of the art, with a follow up talk in 2013 (https://youtu.be/KL-I3-C-KBk https://youtu.be/KL-I3-C-KBk). Both of them mention how Intel is sinking billions of dollars into ASML to try and get this process working, and how impossible everyone thinks it is, so I'm skeptical that they finally got everything squared away now :)
- deepnotderp 7y agoTSMC and Samsung are also exploring EUV, so it's not just Intel. New lithography is necessary to continue shrinking, otherwise mask costs will rise exponentially (literally).
- tlb 7y agoCan you explain the exponential rise in mask costs with shrinking? My naive understanding is that you simply can't resolve features below some fraction of the wavelength. How do more expensive masks get beyond that?
- blp 7y agoI can split any small pitch exposure into separate, larger pitch exposures. For instance, if I need 40nm pitch, and my system is limited to 80nm, I can do 4 exposures. The next shrink requires 8. To figure this out, draw a square, and each node is an exposure. This process works forever in theory, but is limited in practice by the mutual registration of the exposures.
- testvox 7y agoWhat you can do is basically use partially overlapping beams to energize an area smaller than any of the individual beams (think venn diagram). Its a similar technique (except in 2 dimensions) to radiation therapy where multiple beams of radiation are passed through healthy tissue such that their intersection point is on cancerous tissue. That way only the cancerous tissue receives a highly damaging dose of radiation while the healthy tissue receives significantly lesser dosages.
- techsin101 7y agoWhat if we utilized the 3rd dimension just a wild idea. Also designed chips as long rectangular, more surface area.
- lorenzq 7y agoHeat dissipation is the killer
- hevi_jos 7y agoIt is used. 3d stacking is called. Most memory devices, like pendrives use that.
- gameswithgo 7y agowe have been in various ways for a long time. as you stack higher and higher it gets harder to get the heat out, and its already really tough to get the heat out. Like intel's fastest gaming processor, the 9900k, the major difference is better heat dissipation material between the die and heat spreader. laptops and phones are mostly all thermally limited die shrinks help with this, but only if you don't increase performance as you do it.