10 ms·

A Look at the AMD Zen 2 Core

209 points by matt_d 7y ago

deleted 7y ago
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rrss 7y ago
This isn't directly related to Zen 2 (sorry), but it's something I've been wondering about: How do processors that split ops into uops implement precise interrupts? I sort of understand how the ROB is used to implement precise interrupts even with pipelining and OOO, but I don't quite see how processors map uops back to the original instruction sequence.
- strmpnk 7y ago
  I'm not an expert but I believe what accomplishes this task is the reorder buffer. This allows the instruction execution and its side effects to be separated.
  - tempguy9999 7y ago
    The parent's ROB is the reorder buffer. AIUI it causes the instructions to be retired in order (with exceptions stored until retirement, then exposed). The original question, though is how a particular u-op is mapped back to the original macro-instruction, so we know what macro-instruction excepted. And I don't know. I guess is if each u-op is tagged with the instruction address within the process, that would do, but that's carrying around at least 32 bits, which is quite a large tag. Alternatively tag indirectly, which is more likely (you can have maybe 256 instructions 'hot' at any time so an 8-bit tag on each u-op pointing to a 32 or 64-bit table entry (edit: holding the actual address of the macro-op). And the window for the ROB and the other thing that does instruction issue, is ~200 instructions, so that sounds more plausible). All speculation on my part though!
    - strmpnk 7y ago
      I see what they mean then. I read the question a bit too fast. I was mostly assuming that the issue of the operation reserved a spot in the outstanding buffer which would ensure sequencing of the write or commit after execution which would walk through the buffer in sequence. But you're right that there are still more questions to how some of that data is tracked through the pipeline.
    - atq2119 7y ago
      Perhaps there are two copies of the program pointer, one at the "top of the pipe" updated by instruction decode and branch prediction, and one at the "bottom of the pipe" updated by the ROB. Then uops only need to carry the amount by which the program counter is advanced, and certain events can cause a pipeline flush and copy the bottom of pipe version of the counter to the top of the pipe. But that's also all speculation :)
      - tempguy9999 7y ago
        > But that's also all speculation :) How appropriate! But, your idea I think will not work in general where there's branching.
    - Tuna-Fish 7y ago
      Your alternative is sort of close. What happens is that every x86 instruction is assigned a ROB entry. Every uop that has results (stores are handled separately) is assigned a clean register out of the physical register file, and the address of this register (or multiple registers in case of multi-uop instructions) is stored in the corresponding ROB entry. The ROB acts like an in-order circular list -- the retire phase drains it in order from the oldest first, retiring the oldest instruction if and only if all the corresponding PRF registers have been written to. This is the point where any and all side-effects are made visible.
      - tempguy9999 7y ago
        I realise you're describing a dataflow engine. Suddenly it's starting to fall into place. Tomasulo's algorithm (which this is about?) is starting to fall into place. Which is a) amazing and b) OMG the frigging complexity of something that has to run at sub-ns speeds. It's like sausages, the closer you look the less there is to enjoy. Thanks!
      - rrss 7y ago
        Thanks. The bit im not sure about is how to prevent ending up Ina state in the middle of a single instruction if one instruction gets split into multiple uops. Like if one instruction gets split into two uops and the first one completes but the second one raises an exception.
        tempguy9999 7y ago
        OK, let me try (Tuna-Fish, put me right at any point). > Like if one instruction gets split into two uops and the first one completes but the second one raises an exception. That's not a problem. It's just one of n exception types that instruction can raise. Suppose a macro (say x64 instruction, if something like this exists) division instruction where one operand could be fetched from memory, you could have r2 <- r3 / ^r4 where ^r4 fetches the contents of memory at address held in r4. suppose it's split up into u-ops tr6 <- ^r4 ;; tr6 is temporary register 6, invisible to programmer r2 <- r3 / tr6 you could have a division by zero at u-op 2, or an invalid address exception for u-op 1. Either of those are valid exceptions for the original single macro-op. Extrapolating from what Tuna-Fish said, the ROB is list of macro instructions, each instruction I assume will be tagged with its actual macro-op address, and each u-op must link back to the originating macro-op so macro-op retirement can take place, so we have a small (8 bit? Because ROB queue is small) pointer from each u-op back into the macro-op in the ROB. Follow the 8-bit u-op ptr to the ROB, get the originating macro-op address, raise exception at that address. Assuming I'm right, and assuming I understood you question correctly. I'll have to read his answer more carefully again. edit: swapped ^ for asterisk as deref operation, as stars interpreted as formatting. Edit 2: slightly clearer.
- _chris_ 7y ago
  First, most uops can't throw exceptions, so fusing a shift and an add instruction together doesn't require any complex tracking here. If a uop throws an exception (let's say a fused add+ld), each uop can have a tag that helps you backtrace to its PC (instruction address) of let's say the start of the sequence, so you know what to inform the Privileged Architecture as to what "instruction" excepted. For many reasons, you need to store a list of PCs of the inflight instructions somewhere (although it is heavily compressed), so having a small ID tag to help reconstruct a given uop's PC isn't too onerous. Ideally, multiple instructions may map to a single uop, but either none (or up to one) can throw an exception. The hard one here is something like load-pair uops; since each load can throw an exception. Some machines, if a fault is encountered, will refetch the pair and re-execute as independent/unfused loads. Other designs will just pay the pain of tracking which of the pair excepted and do some simple arithmetic off of that.
  - fulafel 7y ago
    Instructions such as shift and add that have memory operands can throw exceptions on x86/amd64. (This was some of the motivations of RISC, separating loads/stores from ALU ops made exception handling cleaner). Heh, random note, I just looked up shift instructions on x86, there are 6 different ones, not RISC. But today there's a lot over 1000 instructions so a few shift variants are peanuts.
    - fulafel 7y ago
      Correcting myself, the issue was uops and not instructions. But this turns out to be still similar: at least intel nowadays keeps the memory addressing part in uops (most cases) and doesn't split instructions into load/store uops + alu ops.
      - monocasa 7y ago
        I thought there was two different uop ISAs on big x86 cores with two different purposes these days. One is pretty close to the original instructions, just decoded and fixed width (on AMD at least, this is what's in the uCode ROM). Then those are cracked to another ISA that the ROB knows about because instructions will cross functional unit boundaries. So in say 'rol mem_addr, shift', your inner ISA would be cracked to something like. ld reg_temp0, mem_addr rol reg_temp0, shift st reg_temp0, mem_addr This is all hearsay though; I could have certainly misheard/misremembered.
- monocasa 7y ago
  My understanding on ISAs that require it is that the uops are marked with the PC of the instruction, and are in the ROB in program order so you can reverse the ROB. Intermediate results aren't fully committed until all of the uops have completed, so there's always the possibility of rollback.
- DSingularity 7y ago
  The simplest solution is a dummy uop “check_int”.
- neerajsi 7y ago
  I'd assume the simplest thing to do would be to flush the pipeline as if you had a branch mispredict, the interrupt can be delivered instead of an alternate branch target.
ademup 7y ago
"Zen employs a dynamic predictor known as a hashed perceptron." When will Hollywood tap into this wealth of cool vocabulary? Is this a gimmicky marketing term, or is it logical\descriptive\rational?
- kkmx 7y ago
  No, it's not a marketing term. That's literally the name of the branch predictor used. See https://www.cs.utexas.edu/~lin/papers/hpca01.pdf https://www.cs.utexas.edu/~lin/papers/hpca01.pdf
- superpermutat0r 7y ago
  Hashed probably means that some features are mapped to a desired perceptron weight via a hash function. This serves as an implicit regularization and can be much more efficient (no need for a predetermined feature vector, sparse representation etc.). It's called hash trick in ML. Perceptron is a single layer NN. Dynamic predictor, a branch predictor that adapts to program input, not just some predetermined state (like a formula that was shown to be good enough for a collection of programs).
  - jnordwick 7y ago
    In this case, I'm pretty sure it means that multiple instruction addreses are hashed to the same perceptron (or is what you said effectively the same thing in ML-speak). Since you don't have branch predictors for each address, you share the same prediction data for multiple addresses (this is one often underlooked cost to heavily branchy code).
- fabianhjr 7y ago
  https://www.wikiwand.com/en/Perceptron https://www.wikiwand.com/en/Perceptron Looks like an already studied technical description going back to 2005: https://github.com/ChampSim/ChampSim/blob/master/branch/hashed_perceptron.bpred https://github.com/ChampSim/ChampSim/blob/master/branch/hash... https://www.jilp.org/cbp2014/paper/DanielJimenez.pdf https://www.jilp.org/cbp2014/paper/DanielJimenez.pdf > Introduced by Tarjan and Skadron 2005 > Basic idea: > - Hash segments of branch history into different tables > - Sum weights selected by hash functions, apply threshold to predict > - Update the weights using perceptron learning https://ieeexplore.ieee.org/document/4492487 https://ieeexplore.ieee.org/document/4492487
bogomipz 7y ago
The post states: >"Perceptrons are the simplest form of machine learning and lend themselves to somewhat easier hardware implementations compared to some of the other machine learning algorithms." Can someone explain what is it about perceptrons that make them easier to implement in hardware?
- StrangeDoctor 7y ago
  All you need for a perceptron is to add up all of the inputs after they’ve been multiplied by their weight. This would probably be done in parallel with a fused multiply add circuit which is fairly simple and some place to store the weights. When they change the perceptron all they need to do is record the current weights and load in the new values.
  - bogomipz 7y ago
    Makes sense, thanks for the explanation.
- matt_d 7y ago
  There's a very approachable explanation in the following (around the 1:01:40 mark): https://youtu.be/8I_1TSs695I?t=1h1m40s https://youtu.be/8I_1TSs695I?t=1h1m40s -- part of Design of Digital Circuits - Lecture 18: Branch Prediction II (ETH Zürich, Spring 2019). Related readings: https://safari.ethz.ch/digitaltechnik/spring2019/doku.php?id=readings#lecture_18_0205_thu https://safari.ethz.ch/digitaltechnik/spring2019/doku.php?id.... These lectures are pretty great, by the way, highly recommended to anyone interested in computer architecture: http://people.inf.ethz.ch/omutlu/lecture-videos.html http://people.inf.ethz.ch/omutlu/lecture-videos.html Incidentally, this year's High-Performance Computer Architecture Test of Time Award has been given to "Dynamic Branch Prediction with Perceptrons" referenced in the lecture (from 2001, https://www.cs.utexas.edu/~lin/papers/hpca01.pdf https://www.cs.utexas.edu/~lin/papers/hpca01.pdf): https://engineering.tamu.edu/news/2019/02/jimenez-receives-high-performance-computer-architecture-test-of-time-award.html https://engineering.tamu.edu/news/2019/02/jimenez-receives-h....
  - 7y ago
deleted 7y ago
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garkin 7y ago
Zen 2 is very good in number crunching and synthetics. But it has a problem - terrible memory latency. 70ns with 3600cl16. (https://www.userbenchmark.com/UserRun/18168279 https://www.userbenchmark.com/UserRun/18168279) It distills to a not-so-good gaming frame times. It's 64mb L3 cache (https://en.wikichip.org/wiki/amd/ryzen_9/3900x https://en.wikichip.org/wiki/amd/ryzen_9/3900x) helps only partially. Few games will suffer greatly from it, but there are several titles with RAM bottlenecks, like PUBG and FarCry. Anyway, AMD has a much better price/performance offer than Intel. For general puprose Intel is totaly anihilated, but for the games they are still more than competitive.
- Zardoz84 7y ago
  if a old and outdated FX8370 can handle modern games, I think that a Zen 2 would not have any problem.
  - cptskippy 7y ago
    I had no issues with an FX-8320e and gaming. I was concerned at first about the memory latency of Zen when I upgrade to a Ryzen R7 1700 but it's been a non issue.
- demilicious 7y ago
  As far as I know, these processors are not yet released. What's the confidence level that this user benchmark will be indicative of real life expected performance? It seems implausible that this user benchmark is a good indicator. The Zen 1 architecture exhibited nothing of the sort[0] -- it would be an order of magnitude performance regression. I expect we'll start to see more accurate tests once the processors are actually released into the wild. [0]https://www.tomshardware.com/reviews/amd-ryzen-7-2700x-review,5571-3.html https://www.tomshardware.com/reviews/amd-ryzen-7-2700x-revie...
  - jchw 7y ago
    Well, to be devil's advocate: just because AMD improved their memory latency does not mean it was state-of-the-art. Indeed, looking at some random user benchmarks of Zen 1, it looks like the memory latency is similar with Zen 1. (See my reply to parent for a couple links, but I think you could also just find random Ryzen 2700X benches and see the same.) Of course, the effects of ~20ns more latency on system memory accesses may not be as easy to observe in practice, especially if throughput is excellent. But we'll see, I guess; 'gaming' benchmarks should be a good test. (Meanwhile, I'm just going to be happy with Zen 2 if it provides a large speedup in compile times.)
mtgx 7y ago
I wish AMD enabled Secure Encrypted Memory by default for all devices, and also bring Secure Encrypted Virtualization (or something similar) to consumer Ryzen chips, too. Even Microsoft has made VM-sandboxing a consumer feature. It's time for AMD to join the bandwagon and help along the way, not keep the virtualization/other security features exclusive to server customers.
- transpute 7y ago
  SEV is claimed to be present on Ryzen Embedded, https://en.wikichip.org/wiki/amd/ryzen_embedded/v1605b#Features https://en.wikichip.org/wiki/amd/ryzen_embedded/v1605b#Featu... Available on UDOO Bolt, https://www.kickstarter.com/projects/udoo/udoo-bolt-raising-the-maker-world-to-the-next-leve https://www.kickstarter.com/projects/udoo/udoo-bolt-raising-... At least AMD made DRTM (SKINIT) available on consumer CPUs, where Intel still keeps DRTM (TXT) limited to business vPro chipsets. ECC is available on some CPU/motherboard/bios combinations for Ryzen, although ECC and low-power for Ryzen APUs is segmented to "Pro" models only available to OEMs. It's still near impossible to buy devices with Ryzen Embedded, despite several system announcements from ASRock, but SEV is available today on Supermicro Epyc 3000 mITX motherboards.
gen3 7y ago
This is a really good article. I am finally at the point in my college education where I can understand what they are talking about! Are there any articles like this about Apple or Intel chips? I like hearing about actual implementations, not just educational processors. (I am looking through the other articles on this site.)
- mixmastamyk 7y ago
  The site has a search function, did ya find anything? I remember Stokes had a recommended book and quite a few articles on Ars Technica back in the day. Covering older hardware, but typically a prereq in understanding newer compatible designs.
- pkaye 7y ago
  Check out the WikiChip tops level page. Covers both Intel, AMD, and ARM. Nothing particular to Apple though. https://en.wikichip.org/wiki/WikiChip https://en.wikichip.org/wiki/WikiChip Also a great book though maybe dated by now is Modern Processor Design by Shen.
- mtone 7y ago
  https://www.anandtech.com https://www.anandtech.com (Ian Cutress et al.) has good regular "deep dive" pieces. David Kanter at https://www.realworldtech.com https://www.realworldtech.com is worth a read, although his site is not as active.
m3kw9 7y ago
Man, just tell me how fast it runs on practical apps.
- topspin 7y ago
  You don't have long to wait. Zen 2 goes retail tomorrow, so the embargo on benchmarks ends and a bunch of reporting from the usual suspects will appear.
- topspin 7y ago
  The verdict is in. Aside from games Ryzen 3000 is a big win; "practical" application run substantially faster on these CPUs. Intel still has a small absolute lead for a bunch of traditional gaming benchmarks, but work loads like compression, rendering, compiling, transcoding are nearly all faster than anything Intel offers. Expect large price cuts from Intel soon.
  - dispat0r 7y ago
    And except games means if you are CPU limited at 1080p or lower with old game engines you are losing maybe 5% performance.

209 points by matt_d 7y ago

deleted 7y ago

[deleted]

rrss 7y ago

This isn't directly related to Zen 2 (sorry), but it's something I've been wondering about: How do processors that split ops into uops implement precise interrupts? I sort of understand how the ROB is used to implement precise interrupts even with pipelining and OOO, but I don't quite see how processors map uops back to the original instruction sequence.

strmpnk 7y ago
I'm not an expert but I believe what accomplishes this task is the reorder buffer. This allows the instruction execution and its side effects to be separated.
- tempguy9999 7y ago
  The parent's ROB is the reorder buffer. AIUI it causes the instructions to be retired in order (with exceptions stored until retirement, then exposed). The original question, though is how a particular u-op is mapped back to the original macro-instruction, so we know what macro-instruction excepted. And I don't know. I guess is if each u-op is tagged with the instruction address within the process, that would do, but that's carrying around at least 32 bits, which is quite a large tag. Alternatively tag indirectly, which is more likely (you can have maybe 256 instructions 'hot' at any time so an 8-bit tag on each u-op pointing to a 32 or 64-bit table entry (edit: holding the actual address of the macro-op). And the window for the ROB and the other thing that does instruction issue, is ~200 instructions, so that sounds more plausible). All speculation on my part though!
  - strmpnk 7y ago
    I see what they mean then. I read the question a bit too fast. I was mostly assuming that the issue of the operation reserved a spot in the outstanding buffer which would ensure sequencing of the write or commit after execution which would walk through the buffer in sequence. But you're right that there are still more questions to how some of that data is tracked through the pipeline.
  - atq2119 7y ago
    Perhaps there are two copies of the program pointer, one at the "top of the pipe" updated by instruction decode and branch prediction, and one at the "bottom of the pipe" updated by the ROB. Then uops only need to carry the amount by which the program counter is advanced, and certain events can cause a pipeline flush and copy the bottom of pipe version of the counter to the top of the pipe. But that's also all speculation :)
    - tempguy9999 7y ago
      > But that's also all speculation :) How appropriate! But, your idea I think will not work in general where there's branching.
  - Tuna-Fish 7y ago
    Your alternative is sort of close. What happens is that every x86 instruction is assigned a ROB entry. Every uop that has results (stores are handled separately) is assigned a clean register out of the physical register file, and the address of this register (or multiple registers in case of multi-uop instructions) is stored in the corresponding ROB entry. The ROB acts like an in-order circular list -- the retire phase drains it in order from the oldest first, retiring the oldest instruction if and only if all the corresponding PRF registers have been written to. This is the point where any and all side-effects are made visible.
    - tempguy9999 7y ago
      I realise you're describing a dataflow engine. Suddenly it's starting to fall into place. Tomasulo's algorithm (which this is about?) is starting to fall into place. Which is a) amazing and b) OMG the frigging complexity of something that has to run at sub-ns speeds. It's like sausages, the closer you look the less there is to enjoy. Thanks!
    - rrss 7y ago
      Thanks. The bit im not sure about is how to prevent ending up Ina state in the middle of a single instruction if one instruction gets split into multiple uops. Like if one instruction gets split into two uops and the first one completes but the second one raises an exception.
      - tempguy9999 7y ago
        OK, let me try (Tuna-Fish, put me right at any point). > Like if one instruction gets split into two uops and the first one completes but the second one raises an exception. That's not a problem. It's just one of n exception types that instruction can raise. Suppose a macro (say x64 instruction, if something like this exists) division instruction where one operand could be fetched from memory, you could have r2 <- r3 / ^r4 where ^r4 fetches the contents of memory at address held in r4. suppose it's split up into u-ops tr6 <- ^r4 ;; tr6 is temporary register 6, invisible to programmer r2 <- r3 / tr6 you could have a division by zero at u-op 2, or an invalid address exception for u-op 1. Either of those are valid exceptions for the original single macro-op. Extrapolating from what Tuna-Fish said, the ROB is list of macro instructions, each instruction I assume will be tagged with its actual macro-op address, and each u-op must link back to the originating macro-op so macro-op retirement can take place, so we have a small (8 bit? Because ROB queue is small) pointer from each u-op back into the macro-op in the ROB. Follow the 8-bit u-op ptr to the ROB, get the originating macro-op address, raise exception at that address. Assuming I'm right, and assuming I understood you question correctly. I'll have to read his answer more carefully again. edit: swapped ^ for asterisk as deref operation, as stars interpreted as formatting. Edit 2: slightly clearer.
_chris_ 7y ago
First, most uops can't throw exceptions, so fusing a shift and an add instruction together doesn't require any complex tracking here. If a uop throws an exception (let's say a fused add+ld), each uop can have a tag that helps you backtrace to its PC (instruction address) of let's say the start of the sequence, so you know what to inform the Privileged Architecture as to what "instruction" excepted. For many reasons, you need to store a list of PCs of the inflight instructions somewhere (although it is heavily compressed), so having a small ID tag to help reconstruct a given uop's PC isn't too onerous. Ideally, multiple instructions may map to a single uop, but either none (or up to one) can throw an exception. The hard one here is something like load-pair uops; since each load can throw an exception. Some machines, if a fault is encountered, will refetch the pair and re-execute as independent/unfused loads. Other designs will just pay the pain of tracking which of the pair excepted and do some simple arithmetic off of that.
- fulafel 7y ago
  Instructions such as shift and add that have memory operands can throw exceptions on x86/amd64. (This was some of the motivations of RISC, separating loads/stores from ALU ops made exception handling cleaner). Heh, random note, I just looked up shift instructions on x86, there are 6 different ones, not RISC. But today there's a lot over 1000 instructions so a few shift variants are peanuts.
  - fulafel 7y ago
    Correcting myself, the issue was uops and not instructions. But this turns out to be still similar: at least intel nowadays keeps the memory addressing part in uops (most cases) and doesn't split instructions into load/store uops + alu ops.
    - monocasa 7y ago
      I thought there was two different uop ISAs on big x86 cores with two different purposes these days. One is pretty close to the original instructions, just decoded and fixed width (on AMD at least, this is what's in the uCode ROM). Then those are cracked to another ISA that the ROB knows about because instructions will cross functional unit boundaries. So in say 'rol mem_addr, shift', your inner ISA would be cracked to something like. ld reg_temp0, mem_addr rol reg_temp0, shift st reg_temp0, mem_addr This is all hearsay though; I could have certainly misheard/misremembered.
monocasa 7y ago
My understanding on ISAs that require it is that the uops are marked with the PC of the instruction, and are in the ROB in program order so you can reverse the ROB. Intermediate results aren't fully committed until all of the uops have completed, so there's always the possibility of rollback.
DSingularity 7y ago
The simplest solution is a dummy uop “check_int”.
neerajsi 7y ago
I'd assume the simplest thing to do would be to flush the pipeline as if you had a branch mispredict, the interrupt can be delivered instead of an alternate branch target.

ademup 7y ago

"Zen employs a dynamic predictor known as a hashed perceptron." When will Hollywood tap into this wealth of cool vocabulary? Is this a gimmicky marketing term, or is it logical\descriptive\rational?

kkmx 7y ago
No, it's not a marketing term. That's literally the name of the branch predictor used. See https://www.cs.utexas.edu/~lin/papers/hpca01.pdf https://www.cs.utexas.edu/~lin/papers/hpca01.pdf
superpermutat0r 7y ago
Hashed probably means that some features are mapped to a desired perceptron weight via a hash function. This serves as an implicit regularization and can be much more efficient (no need for a predetermined feature vector, sparse representation etc.). It's called hash trick in ML. Perceptron is a single layer NN. Dynamic predictor, a branch predictor that adapts to program input, not just some predetermined state (like a formula that was shown to be good enough for a collection of programs).
- jnordwick 7y ago
  In this case, I'm pretty sure it means that multiple instruction addreses are hashed to the same perceptron (or is what you said effectively the same thing in ML-speak). Since you don't have branch predictors for each address, you share the same prediction data for multiple addresses (this is one often underlooked cost to heavily branchy code).
fabianhjr 7y ago
https://www.wikiwand.com/en/Perceptron https://www.wikiwand.com/en/Perceptron Looks like an already studied technical description going back to 2005: https://github.com/ChampSim/ChampSim/blob/master/branch/hashed_perceptron.bpred https://github.com/ChampSim/ChampSim/blob/master/branch/hash... https://www.jilp.org/cbp2014/paper/DanielJimenez.pdf https://www.jilp.org/cbp2014/paper/DanielJimenez.pdf > Introduced by Tarjan and Skadron 2005 > Basic idea: > - Hash segments of branch history into different tables > - Sum weights selected by hash functions, apply threshold to predict > - Update the weights using perceptron learning https://ieeexplore.ieee.org/document/4492487 https://ieeexplore.ieee.org/document/4492487

bogomipz 7y ago

The post states: >"Perceptrons are the simplest form of machine learning and lend themselves to somewhat easier hardware implementations compared to some of the other machine learning algorithms." Can someone explain what is it about perceptrons that make them easier to implement in hardware?

StrangeDoctor 7y ago
All you need for a perceptron is to add up all of the inputs after they’ve been multiplied by their weight. This would probably be done in parallel with a fused multiply add circuit which is fairly simple and some place to store the weights. When they change the perceptron all they need to do is record the current weights and load in the new values.
- bogomipz 7y ago
  Makes sense, thanks for the explanation.
matt_d 7y ago
There's a very approachable explanation in the following (around the 1:01:40 mark): https://youtu.be/8I_1TSs695I?t=1h1m40s https://youtu.be/8I_1TSs695I?t=1h1m40s -- part of Design of Digital Circuits - Lecture 18: Branch Prediction II (ETH Zürich, Spring 2019). Related readings: https://safari.ethz.ch/digitaltechnik/spring2019/doku.php?id=readings#lecture_18_0205_thu https://safari.ethz.ch/digitaltechnik/spring2019/doku.php?id.... These lectures are pretty great, by the way, highly recommended to anyone interested in computer architecture: http://people.inf.ethz.ch/omutlu/lecture-videos.html http://people.inf.ethz.ch/omutlu/lecture-videos.html Incidentally, this year's High-Performance Computer Architecture Test of Time Award has been given to "Dynamic Branch Prediction with Perceptrons" referenced in the lecture (from 2001, https://www.cs.utexas.edu/~lin/papers/hpca01.pdf https://www.cs.utexas.edu/~lin/papers/hpca01.pdf): https://engineering.tamu.edu/news/2019/02/jimenez-receives-high-performance-computer-architecture-test-of-time-award.html https://engineering.tamu.edu/news/2019/02/jimenez-receives-h....
- 7y ago

deleted 7y ago

[deleted]

garkin 7y ago

Zen 2 is very good in number crunching and synthetics. But it has a problem - terrible memory latency. 70ns with 3600cl16. (https://www.userbenchmark.com/UserRun/18168279 https://www.userbenchmark.com/UserRun/18168279) It distills to a not-so-good gaming frame times. It's 64mb L3 cache (https://en.wikichip.org/wiki/amd/ryzen_9/3900x https://en.wikichip.org/wiki/amd/ryzen_9/3900x) helps only partially. Few games will suffer greatly from it, but there are several titles with RAM bottlenecks, like PUBG and FarCry. Anyway, AMD has a much better price/performance offer than Intel. For general puprose Intel is totaly anihilated, but for the games they are still more than competitive.

Zardoz84 7y ago
if a old and outdated FX8370 can handle modern games, I think that a Zen 2 would not have any problem.
- cptskippy 7y ago
  I had no issues with an FX-8320e and gaming. I was concerned at first about the memory latency of Zen when I upgrade to a Ryzen R7 1700 but it's been a non issue.
demilicious 7y ago
As far as I know, these processors are not yet released. What's the confidence level that this user benchmark will be indicative of real life expected performance? It seems implausible that this user benchmark is a good indicator. The Zen 1 architecture exhibited nothing of the sort[0] -- it would be an order of magnitude performance regression. I expect we'll start to see more accurate tests once the processors are actually released into the wild. [0]https://www.tomshardware.com/reviews/amd-ryzen-7-2700x-review,5571-3.html https://www.tomshardware.com/reviews/amd-ryzen-7-2700x-revie...
- jchw 7y ago
  Well, to be devil's advocate: just because AMD improved their memory latency does not mean it was state-of-the-art. Indeed, looking at some random user benchmarks of Zen 1, it looks like the memory latency is similar with Zen 1. (See my reply to parent for a couple links, but I think you could also just find random Ryzen 2700X benches and see the same.) Of course, the effects of ~20ns more latency on system memory accesses may not be as easy to observe in practice, especially if throughput is excellent. But we'll see, I guess; 'gaming' benchmarks should be a good test. (Meanwhile, I'm just going to be happy with Zen 2 if it provides a large speedup in compile times.)

mtgx 7y ago

I wish AMD enabled Secure Encrypted Memory by default for all devices, and also bring Secure Encrypted Virtualization (or something similar) to consumer Ryzen chips, too. Even Microsoft has made VM-sandboxing a consumer feature. It's time for AMD to join the bandwagon and help along the way, not keep the virtualization/other security features exclusive to server customers.

transpute 7y ago
SEV is claimed to be present on Ryzen Embedded, https://en.wikichip.org/wiki/amd/ryzen_embedded/v1605b#Features https://en.wikichip.org/wiki/amd/ryzen_embedded/v1605b#Featu... Available on UDOO Bolt, https://www.kickstarter.com/projects/udoo/udoo-bolt-raising-the-maker-world-to-the-next-leve https://www.kickstarter.com/projects/udoo/udoo-bolt-raising-... At least AMD made DRTM (SKINIT) available on consumer CPUs, where Intel still keeps DRTM (TXT) limited to business vPro chipsets. ECC is available on some CPU/motherboard/bios combinations for Ryzen, although ECC and low-power for Ryzen APUs is segmented to "Pro" models only available to OEMs. It's still near impossible to buy devices with Ryzen Embedded, despite several system announcements from ASRock, but SEV is available today on Supermicro Epyc 3000 mITX motherboards.

gen3 7y ago

This is a really good article. I am finally at the point in my college education where I can understand what they are talking about! Are there any articles like this about Apple or Intel chips? I like hearing about actual implementations, not just educational processors. (I am looking through the other articles on this site.)

mixmastamyk 7y ago
The site has a search function, did ya find anything? I remember Stokes had a recommended book and quite a few articles on Ars Technica back in the day. Covering older hardware, but typically a prereq in understanding newer compatible designs.
pkaye 7y ago
Check out the WikiChip tops level page. Covers both Intel, AMD, and ARM. Nothing particular to Apple though. https://en.wikichip.org/wiki/WikiChip https://en.wikichip.org/wiki/WikiChip Also a great book though maybe dated by now is Modern Processor Design by Shen.
mtone 7y ago
https://www.anandtech.com https://www.anandtech.com (Ian Cutress et al.) has good regular "deep dive" pieces. David Kanter at https://www.realworldtech.com https://www.realworldtech.com is worth a read, although his site is not as active.

m3kw9 7y ago

Man, just tell me how fast it runs on practical apps.

topspin 7y ago
You don't have long to wait. Zen 2 goes retail tomorrow, so the embargo on benchmarks ends and a bunch of reporting from the usual suspects will appear.
topspin 7y ago
The verdict is in. Aside from games Ryzen 3000 is a big win; "practical" application run substantially faster on these CPUs. Intel still has a small absolute lead for a bunch of traditional gaming benchmarks, but work loads like compression, rendering, compiling, transcoding are nearly all faster than anything Intel offers. Expect large price cuts from Intel soon.
- dispat0r 7y ago
  And except games means if you are CPU limited at 1080p or lower with old game engines you are losing maybe 5% performance.