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AMD Zen 2 Microarchitecture Analysis: Ryzen 3000 and EPYC Rome
- keyle 7y agoI find these articles incredible, but then I remember I work and live on a Mac. And I can't wait to pay 5K for the content of one of those articles published 2 years ago.
- kbenson 7y ago> And I can't wait to pay 5K for the content of one of those articles published 2 years ago. Err, "can't wait" as in "it will be awesome when it arrives" or as in "I'm not going to wait for that, stupid Apple"?
- kyriakos 7y agoI think the OP sarcasm was obvious.
- kbenson 7y agoI thought it was likely, but I also thought the wording ("for the content of one of those articles") was weird enough that I was confused. I think what was meant was "And I can't wait to pay 5K for the hardware described in one of those articles published 2 years ago." Also, I would be a lot more confident in labeling it sarcasm if I didn't believe there were plenty of people actually eagerly awaiting new Apple hardware just like that. In any case, Poe's law strikes again.
- deleted 7y ago[deleted]
- thirdsun 7y agoSame here. I'd love to build a Ryzen box, and actually I'll do so for gaming, but my primary computer has to run macOS and unfortunately that requirement comes with a significant price tag, in addition to outdated hardware.
- heyoni 7y agoCan’t you do hackintoshes with Ryzen?
- unicornfinder 7y agoNot without a lot of messing around. With Intel you can pretty much just straight install macOS + Clover + FakeSMC and you're golden. With Ryzen you have to start messing around with custom kernels, which means updates will break things and also means a lot of programs won't work. Last I checked a lot of progress had been made, but you're unable to run any 32-bit applications and some software such as the Adobe Creative Suite simply won't run.
- mrgreenfur 7y agoI too thought it was hard, but recently found this that supposedly makes it way easier: https://kb.amd-osx.com/guides/HS/ https://kb.amd-osx.com/guides/HS/ I'm considering a new ryzen hackintosh build in july!
- andy_ppp 7y agoI worry a bit about stability...
- tracker1 7y agoGoing to give it one, single try... then I'm on to Linux as my primary. Will have a Windows VM for some work, and may keep a mac VM as well. Most of the stuff I do works fine in Linux, and it really looks like Manjaro and Pop_OS! have made a lot of progress beyond the general dev stuff I work on (mostly via Docker/Linux anyway).
- nabla9 7y agoApple hardware functions as a software protection dongle. If you want to use Apple software you must buy a dongle.
- Synaesthesia 7y agoExcept if you hackintosh
- Ragib_Zaman 7y agoI guess I was being ridiculously optimistic hoping for the 16 core chip to be around the $600 mark :(
- CriticalCathed 7y ago750 is pretty close at least.
- jchw 7y agoOn the other hand, a 12C with a handsome IPC improvement from last generation at $499 feels pretty tempting to me...
- gravypod 7y agoYou can also buy into TR4 Threadripper 1950x for ~$500 [0]. I'm using one to write this post. It's a great system and you can likely buy used for cheaper than $500. I'm also assuming this price will fall further once they announce another TR4 chip. [0] - https://www.amazon.com/AMD-Threadripper-32-thread-Processor-YD195XA8AEWOF/dp/B074CBH3R4 https://www.amazon.com/AMD-Threadripper-32-thread-Processor-...
- opencl 7y agoI think the whole system price basically ends up as a wash with TR4 motherboards being at least ~$300 and needing a ~$100 cooler, I'm assuming these consumer chips will continue to have bundled coolers. The 3950X also draws 75W less than the 1950X so you can probably save a few bucks on the power supply and of course your electric bills over time. The performance comparison will be interesting though. The 3950X should be quite a bit faster than the 1950X when it's not bottlenecked by memory bandwidth, but of course the 1950X still has twice the memory channels. Slightly offset by the Zen2 memory controller supporting higher frequency RAM. So which one is better will depend heavily on workload. I suspect that for a developer workstation the 3950X would be the better performer, most compilation workloads are not very sensitive to bandwidth.
- 7y ago
- craz8 7y agoIt looks like Microsoft is adding code to Windows to schedule threads in a way that works with this configuration of cores and CCXs Is/has Linux added similar code Are we calling this Mini-Numa or something else?
- shereadsthenews 7y agoWhy would we call it “mini”? It is straight up NUMA.
- wmf 7y agoIt's not NUMA since the distance from all the cores to main memory is the same (uniform).
- shereadsthenews 7y agoOh hrmm, my mistake. This is a welcome change from the older one.
- craz8 7y agoAlthough Threadripper 2990 is not uniform to main memory, which adds a wrinkle So now there’s at least 2 levels of Non Uniform access to manage by the Bios/OS
- Dylan16807 7y agoDon't forget the CCX level, too. The full list of varying latencies is something like: SMT, inter-core, inter-CCX, inter-die, inter-socket. And even that misses a few subtleties.
- wmf 7y agoI would call it a form of Non-Uniform Cache Architecture (NUCA). Linux definitely knows the cache topology and the scheduler is NUMA-aware but I don't know if the scheduler takes cache topology into account. It seems like it would be a small change to track L3s instead of NUMA nodes.
- shereadsthenews 7y agoThe BTB was the real problem with Naples and the reason it sucked on non-trivial, branchy, pointer-chasing workloads like MySQL. With the improved branch prediction resources I’ll be interested in head-to-head of this rig vs. a Kaby Lake (or later).
- ahartmetz 7y agoSounds interesting and I don't recall reading that before - can you point to some online article about it?
- jnordwick 7y agoAlso AMDs often smaller cache sizes, which still seems to be a problem if you compare to ice lake and above.
- opencl 7y agoWhat? Zen/Zen+ had larger L1 icache than Intel, same size L1 dcache and L2 and L3. Zen 2 actually decreases the L1 icache to 32KB but in exchange increases L1 associativity, micro-op cache size, BTB size, and L3 size.
- shereadsthenews 7y agoZen’s gigantic cache wasn’t very effective on account of the way it is arranged in itty bitty little shards.
- zrm 7y ago8MB is itty bitty? There are a few narrow workloads where having a huge unified cache is an advantage, but it generally isn't. If you have many independent processes or VMs it can actually be worse, because when you have one thrashing the caches it would ruin performance across the whole processor rather than being isolated to a subset. Meanwhile most working sets either fit into 8MB or don't fit into 64MB. When you have a 4MB working set it makes no difference and when you have a 500GB one it's the difference between a >99% miss rate and a marginally better but still >99% miss rate. Where it really matters is when you have a working set which is ~16MB and then the whole thing fits in one case but not the other. But that's not actually that common, and even in that case it's no help if you're running multiple independent processes because then they each only get their proportionate share of the cache anyway. So the difference is really limited to a narrow class of applications with a very specific working set size and little cache contention between separate threads/processes.
- wahern 7y agoAnybody expect 7nm processes to result in longevity issues? As far as I understand (and IME) the first components to fail are capacitors. Might that begin to change? Apropos the article, I'm trying to convince myself to build an EPYC 3201 server now rather than waiting for the Zen 2 version, for which I presume I'd have to wait until October or November at the earliest.
- ngold 7y agoFirst generation anything is not as good as it's going to be.
- jdsully 7y agoUp until recently every CPU generation was on a brand new node - there was no second gen on the same process. We never had reliability issues with CPUs before.
- dfrage 7y agoThe Intel Atom C2000 product family had a terrible problem which would brick systems, see for example https://www.tomshardware.com/news/intel-cpu-failure-atom-processor,33538.html https://www.tomshardware.com/news/intel-cpu-failure-atom-pro... or https://www.theregister.co.uk/2017/02/06/cisco_intel_decline_to_link_product_warning_to_faulty_chip/ https://www.theregister.co.uk/2017/02/06/cisco_intel_decline...
- deleted 7y ago[deleted]
- jdsully 7y agoThere was also a weak transistor on some Sandy Bridge chips in the SATA controller. But these failures are really quite rare.
- baybal2 7y agoI think, electromigration will still kill the chip earlier than individual device failures. It was Intel is said to switched to cobalt wiring in latest node, and seems to be paying dearly for that. TSMC and others seem to go the conventional road and continued to perfect the salicide for smaller nodes without any issues.
- microcolonel 7y agoIt was fun seeing their materials refer to their branch predictor as a TAGE predictor. I remember hearing about the original paper for that when I was too young and inexperienced to focus long enough to understand it; then I saw a TAGE predictor show up in Chris Celio's BOOM repository, and I read it through. If what AMD says is true, the new (for them) TAGE predictor in their industry-leading microarchitecture having 30% fewer branch mispredictions than the last, it feels very cool that one can read and somewhat anderstand the operation of a similar predictor in the leisure hours of a few days. Also those caches are huge, wow.
- kjeetgill 7y agoIt took a little hunting, is this the paper? http://www.irisa.fr/caps/people/seznec/JILP-COTTAGE.pdf http://www.irisa.fr/caps/people/seznec/JILP-COTTAGE.pdf
- gpderetta 7y agoInteresting; Intel is rumored to use TAGE but it was never confirmed officially. AMD claimed to use a perceptron based predictor in the past.
- emn13 7y agoThey still will, just for L1 only; TAGE is for the lower levels.
- walterbell 7y ago> ... for the issues to which AMD is vulnerable, it has implemented a full hardware-based security platform for them. The change here comes for the Speculative Store Bypass, known as Spectre v4, which AMD now has additional hardware to work in conjunction with the OS or virtual memory managers such as hypervisors in order to control. AMD doesn’t expect any performance change from these updates. Which Intel CPU generation will have hardware fixes for these Spectre variants?
- baybal2 7y agoI guess it will score it a lot of datacentre business. Not so few big "cloud" providers still run completely bare with regards to microcode patches, and some very likely do so intentionally.
- masklinn 7y agoWhat do you mean by "run completely bare with regards to microcode patches", that they don't apply microcode patches & errata?
- baybal2 7y agoYes, that they did not bring up microcode patches that cover some of Spectre/Meltdown family bugs
- zeroname 7y agoDo you have a source for that?
- dijit 7y agoGCP was "fully fixed before it was known" according to the engineers I know there. I find it /highly/ unlikely that they don't have patched microcode. I mean, the cloud business is the place with the most to lose from these kinds of issues, I am incredibly suspicious of the claim that cloud providers aren't patching their microcode. Whether it's intels or their own modified variant of microcode I would fully expect them to be patched in some way.
- fitnesshealth 7y agoAnother article on https://www.follownews.com/amd-zen-2-microarchitecture-analysis-ryzen-3000-and-epyc-rome-5sy17 https://www.follownews.com/amd-zen-2-microarchitecture-analy...
- psnosignaluk 7y ago$499 for 12C/24T on the 3900X? $399 for 8C/16T on the 3800X? Those prices make this a very tempting chipset on top of the promised performance being touted by AMD. Looking forward to seeing the reviews and news on X570 boards. Hopefully the manufacturers will be plugging in decent features to match their threats of massive price hikes on AM4 boards with the new chipset.
- sliken 7y agoRumors claimed there would be a 3700 that was 8c/16 64 watts and only slightly slower clocked than the 3700x. It was also supposedly $200 or so (the 3700x is $329). Here's hoping it comes out, looks like a great CPU for a relatively cheap desktop.
- penagwin 7y agoIf the 3700x is $329 I would bet on the 3700 being around $250, at least at launch. ~$80 cheaper is how they currently have it priced, 200$ for a slightly lower clockspeed seems too cheap, and it'd cut into their 3600(X) range.
- horyzen 7y agoBut if you look at the launch price 2700 was $300 and 2700X was $330. I think the difference is so small that it drives people who don't want to manually overclock buy the X version to skip the hassle.
- CoolGuySteve 7y agoFor a single GPU machine, I’m not sure what the use case is for X570 over a much cheaper B450 board. Most games currently aren’t GPU-bus bandwidth limited (or rather the GPU itself is the bottleneck) so I suspect PCIe 4.0 won’t impact benchmarks much.
- tutanchamun 7y agoSince 2 lanes of PCIe4 are as fast as 4 lanes of PCIe3 I think it can make sense for more IO if you don't want to go for Threadripper. On top of that the motherboards I have read about thus far have better VRM setups for the CPU so for overclocking that could make sense as well.
- nottorp 7y agoNow... when will AMD fix power consumption on their video cards as well?
- nottorp 7y agoFunny about those downvotes. AMD can deliver 8C/16T in 65 W but their GPUs need 50%+ more power than nvidia's for the same performance (up to 100% more at the 1080 lower end). You're saying I'm not right and they don't have a problem?
- dave7 7y agoAt this same event they also announced their 1st gen RDNA GPUs, called Navi. Also releasing to retail on July 7th. They supposedly go quite some way to reducing the gulf in GPU power usage/performance.
- officeplant 7y agoGoing by their E3 presentation of the 5700 and 5700 XT last night they haven't done enough to curb power use, but only testing will tell once we have these cards in hand.
- tracker1 7y agoAgreed... I'm a bit torn on this, since they've done a lot for Linux support, may go 5700XT or Radeon VII to pair with 3950X
- paulmd 7y agoNot really. They have finally managed to reach Pascal-level perf/watt... on 7nm, competing against 16nm NVIDIA chips. It's more or less a GTX 1080 competitor as far as performance and perf/watt is concerned. So, roughly 3 years and a node's worth of uarch disadvantage behind NVIDIA. It's a repeat of Vega, where AMD finally managed to reach Maxwell-level perf/watt... on 14nm, competing against 28nm NVIDIA chips. Once again they are years late and too expensive to boot. They've managed to close the gap to Turing a little bit (because NVIDIA is still on a 16+ node rather than 7nm) but it's going to be a bloodbath when NVIDIA ports down to 7nm next year. Price is the great equalizer, but once again AMD is choosing to price head-to-head with NVIDIA. Racing onto 7nm was not a cheap move for them.
- netrikare 7y agoDoes anyone know if AMD is working on supporting transactional memory in their cpus? https://en.wikipedia.org/wiki/Advanced_Synchronization_Facility https://en.wikipedia.org/wiki/Advanced_Synchronization_Facil...
- sorenjan 7y agoHow does new instructions, register renaming, etc work with different compilers? Say I'm using Visual Studio to compile C++, will it take advantage of the new processor features by default? What about if the binary runs on a different CPU, will the compiler include feature checks and multiple code versions?
- horyzen 7y agoNot sure about VC++, but in gcc you can use -march=native to let the compiler compile the code with all instruction sets available on your CPU, I think there is a VC++ equivalent. As for already compiled binary, depending on how it was compiled it may or may not work of a different CPU. Also the compiler doesn't do the runtime checks.
- jjuhl 7y agoGCC can do Function Multi Versioning (https://gcc.gnu.org/wiki/FunctionMultiVersioning https://gcc.gnu.org/wiki/FunctionMultiVersioning , https://lwn.net/Articles/691932/ https://lwn.net/Articles/691932/) where it will generate code for multiple CPUs and select the best at run time.
- ken 7y agoAIUI, register renaming is a runtime feature of the microcode and has nothing to do with the machine language interface.
- mhh__ 7y agoCorrect. The compiler can be trained to utilise it efficiently but it's not a exposed feature
- opencl 7y agoGCC and LLVM have supported multiple code versions based on feature detection for a few years, they call it function multiversioning. As far as I'm aware MSVC does not have this yet.
- choudanu4 7y agoAMD’s primary advertised improvement here is the use of a TAGE predictor, although it is only used for non-L1 fetches. This might not sound too impressive: AMD is still using a hashed perceptron prefetch engine for L1 fetches, which is going to be as many fetches as possible, but the TAGE L2 branch predictor uses additional tagging to enable longer branch histories for better prediction pathways. This becomes more important for the L2 prefetches and beyond, with the hashed perceptron preferred for short prefetches in the L1 based on power. I found this paragraph confusing, is it talking about data prefetchers (Which would make sense b/c of the mention of short prefetches) or branch predictors? (Which would make sense b/c of the mention of TAGE and Perceptron)
- derefr 7y agoA little of both. My understanding of the above paragraph is that the L1 predictor is trying to predict which code-containing cache lines need to stay loaded in L1, and which can be released to L2, by determining which branches from L1 cache-lines to L1 cache-lines are likely to be taken in the near future. Since L1 cache lines are so small, the types of jumps that can even be analyzed successfully have very short jump distances—i.e. either jumps within the same code cache-line, or to its immediate neighbours. The L1 predictor doesn’t bother to guess the behaviour of jumps that would move the code-pointer more than one full cache-line in distance. Or, to put that another way, this reads to me like the probabilistic equivalent of a compiler doing dead code elimination on unconnected basic blocks. The L1 predictor is marking L1 cache lines as “dead” (i.e. LRU) when no recently-visited L1 cache line branch-predicts into them.
- BeeOnRope 7y agoI was also confused by this, but my reading is this is entirely about branch prediction nothing about caching. In that context L1 and L2 simply refer to "first" and "second" level branch prediction strategies, and are not related to the L1 and L2 cache (in the same way that L1 and L2 BTB and L1 and L2 TLB are not related to L1 and L2 cache). The way this works is there a fast predictor (L1) that can make a prediction every cycle, or at worst every two cycles, which initially steers the front end. At the same time, the slow (L2) predictor is also working on a prediction, but it takes longer: either throughput limit (e.g., one prediction every 4 cycles) or with a long latency (e.g., takes 4 cycles from the last update to make a new one). If the slow predictor ends up disagreeing with the fast one, the front end if "re-steered", i.e., repointed to the new path predicted by the slow predictor. This happens only in a few cycles so it is much better than a branch misprediction: the new instructions haven't started executing yet, so it is possible the bubble is entirely hidden, especially if IPC isn't close to the max (as it usually is not). Just a guess though - performance counter events indicate that Intel may use a similar fast/slow mechanism.
- sfink 7y agoThat was a great article. I wonder if fixing the reliability of their performance counters to work with rr ( https://rr-project.org/ https://rr-project.org/ ) is anywhere on their radar. Sadly, until that happens, AMD CPUs are dead to me. For a C++ (or C or Rust) developer, rr is just too much of a productivity boost to give up.
- BuckRogers 7y agoI bought the Ryzen 1700, 1800X and 2700X. Looking to upgrade to one of these, but will wait for benchmarks, AMD is really on a roll. The 3950X is extremely tempting especially considering I can drop it right in my existing AM4 motherboard. Allowing backwards compatibility where possible was the best move they made. I would've bought 1 CPU from them instead of 3 (and soon 4, and then 5 with Zen3), without it.
- simplyinfinity 7y agozen3 would most likely be on a new socket, AFAIK. Zen2+ (4xxx series) would most likely be the last cpu for AM4, as amd have stated they will keep sockets for 4 years but that's OK since intel change it about every year or so.. I myself will be upgrading from 1700X to Either the new 8 core... but the 16 core looks so sweet...
- BuckRogers 7y agoAMD's slides showed Zen3 as the next release (Ryzen 4000 series), as 7nm+/Zen3 in 2020. Zen2+ isn't a thing, unless AMD is simply calling it Zen3. I'm not sure the names matter, as Zen+ was better than I was expecting with the XFR2 changes, so I bought one. From what I can tell, they tied support to DDR4 support. I'm expecting Zen3 next year to be the last AM4 CPU. Doesn't really matter to me, with the value they've been delivering since the original Ryzen launch, I see no reason to not buy them all. People appreciate a good discount on a desirable CPU on Craigslist when its time to upgrade. It's just an easy swap, especially if you use an IC Graphite thermal pad instead of thermal paste.
- caycep 7y agoI wonder if I'm misinterpreting TDP. For the 105W TDP chip vs. say the 65 W one. If there is a lesser task not saturating the cores, the power/heat generation would be similar, and the bigger chip doesn't really ramp up the heat/wattage unless heavier loads are thrown at it?
- dsr_ 7y agoFor sibling chips like this, yes. Two cores being run at 90% utilization each will draw about the same amount of power regardless of whether you bought the 6-core version or the 8-core version. Similarly, 4 cores running on the 12 or 16 core chips should eat about the same amount of power as each other.