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Intel Xeon processor with FPGA now shipping
- arcanus 8y agoCould this be a hint at Intel's supercomputing and AI strategy? They cannot compete with GPUs on flops with Xeon, but an embedded FPGA might get them closer. It is a risky strategy however. Even if they can attain similar performance, which I doubt, programmability remains the big problem for FPGAs. I know Intel is pushing openCL but it simply does not have an ecosystem for software right now, and it remains to be seen if they can even enable much of the feature set of openCL on an FPGA.
- Scaevolus 8y agoXeon Phi coprocessors are flops competitive with GPUs and are used in many supercomputers. Embedded FPGA accelerators are of interest primarily to large server farms and cloud operators, where the cost of development for FPGA acceleration is cheaper than the savings of acceleration-- Microsoft in particular has done a lot of work in this area (for Bing), and probably worked with Intel to define the CPU.
- quadruplebond 8y agoPretty sure that Phi as you know it is largely being left. Argonne's Aurora exascale machine was suppose to be Xeon Phi, but it has been postponed till 2021 and will likely use some other tech. Also look at the top 500 list from late 2017. Trinity the NNSA computer at #7 is Phi based but only gets about 50% of theoretical peak.
- semi-extrinsic 8y agoMy personal tinfoil hat take is that Xeon Phi was made to make China waste top dollar on their supercomputers going with a less useful accelerator made by a US company.
- exikyut 8y agoOnce China figured that out, the way they'd implement not falling for the same trick twice is simply never using US tech again. Which would limit other opportunities. It's also at least plausible that they'd probably have people trained to think like Americans who might think of the same thing in advance.
- ksec 8y agoBy wasting millions of dollar and literally gave the Phi for free to China, which is part of the Intel CPU deal? The answer is rather simple. Xeon Phi wasn't as good as the GPU counterpart.
- ropeadopepope 8y agoNot if you believe Tom Forsyth http://tomforsyth1000.github.io/blog.wiki.html#%5B%5BWhy%20didn%27t%20Larrabee%20fail%3F%5D%5D http://tomforsyth1000.github.io/blog.wiki.html#%5B%5BWhy%20d...
- netheril96 8y agoYes US government has forbidden the export of Xeon and Xeon Phi to China's supercomputing centers. It prompted the construction of Sunway TaihuLight, which uses Chinese own CPUs.
- batbomb 8y agoPhi is dead. The next NERSC computer is GPUs. Not sure what Argonne is doing but there’s no reason to think it won’t be GPUs. The only reason Phi/KNL made sense was because it seemed like a conservative choice when GPUs were more exotic, which may have been okay if Intel didn’t have the crazy yield problems they had. FPGAs don’t make sense because the conservative choice at this point is GPU. I don’t think any of the leading compute facilities have the stomach for a new technology like this, especially from intel.
- llukas 8y agoCmon it wasn't just yield problems. Premise that you can just recompile CPU code and it would run quickly on Phi was false.
- sanxiyn 8y agoIt's a pity. Intel does have a compiler that works great for Xeon Phi: ISPC. Alas, it seems Intel was never serious about ISPC.
- gbrown_ 8y ago> The next NERSC computer is GPUs. Got a source on this? I've not seen an official mention of what sort of architecture NERSC-9 will be. > Not sure what Argonne is doing but there’s no reason to think it won’t be GPUs. It will be a future Intel processor [1]. [1] https://www.hpcwire.com/2017/09/27/us-coalesces-plans-first-exascale-supercomputer-aurora-2021/ https://www.hpcwire.com/2017/09/27/us-coalesces-plans-first-...
- batbomb 8y agoNothing I can link to, but that information has been shared to DOE labs and projects relying on large NERSC allocations.
- deleted 8y ago[deleted]
- vegetablepotpie 8y ago>programmability remains the big problem for FPGAs I agree because there's added levels of complexity with HDLs that SW doesn't have to deal with. What would be nice is if there was a tool that you could declare your problem (functions) and your constraints (throughput, LUTs available) and it would figure out the memory, ALUs and pipe-lining needed to solve the problem.
- meuk 8y agoThat is called high-level synthesis and there are some tools for this available (and I know at least one company who produces a proprietary toolchain - including hardware - for this). In my experience, high-level synthesis makes things a lot easier for the programmer, but you still have to be aware of very low-level details (and you still can get bitten by abstractions that you don't fully understand).
- exikyut 8y agoThat company might fruitfully make their system available within a datacenter / "VPS"-type context, eg the way Cloud9 does it. (https://c9.io/ https://c9.io/, you make a free account, you instantly get a Web based editor connected to a Debian VM) If their system accepts "mostly ordinary" code in eg C, a fair amount of stuff would probably work with it, so it could scale beyond educational exploration/tinkering, too.
- esmi 8y agoLike this? https://www.mathworks.com/solutions/fpga-design.html https://www.mathworks.com/solutions/fpga-design.html
- sannee 8y ago> They cannot compete with GPUs on flops with Xeon, but an embedded FPGA might get them closer. FPGAs aren't known for their FLOPs though. Sure, the high end ones pack a punch, but compared to GPUs are still extremely expensive.
- rjsw 8y agoAltera has hard floating point blocks in their FPGAs, I don't think any other manufacturer does though.
- sannee 8y agoYeah - the best Stratix 10 can do 9.2 TFLOPs. A GTX 1080 Ti can do 11.3 TFLOPs. Now I can't find any price info on those Stratixes, but given how expensive these FPGAs generally get, I highly doubt it will be anywhere near the $700 for a 1080 (and that's for the entire card!). I am not saying these things don't have applications, but the "usual" computational workloads are not one of them.
- sehugg 8y agoFrom The Next Platform (https://www.nextplatform.com/2018/05/24/a-peek-inside-that-intel-xeon-fpga-hybrid-chip/ https://www.nextplatform.com/2018/05/24/a-peek-inside-that-i...): The initial workload that Intel is targeting is putting Open Virtual Switch, the open source virtual switch, on the FPGA, offloading some switching functions in a network from the CPU where such virtual switch software might reside either inside a server virtualization hypervisor or outside of it but alongside virtual machines and containers. This obviates the need for certain Ethernet switches in the kind of Clos networks used by hyperscalers, cloud builders, telcos, and other service providers and also frees up compute capacity on the CPUs that might otherwise be managing virtual switching. Intel says that by implementing Open Virtual Switch on the FPGA, it can cut the latency on the virtual switch in half, boost the throughput by 3.2X, and crank up the number of VMs hosted on a machine by 2X compared to just running Open Virtual Switch on the Xeon portion of this hybrid chip. That makes a pretty good case for having the FPGA right close to the CPU – provided this chip doesn’t cost too much.
- mtgx 8y agoThat seems like a weak benefit. I don't think the fpga part will be cheap. In fact it will probably be significantly more expensive than the CPU. So then why not buy a chip with twice the cores if running twice the VMs is what you want to do with it? Also you can buy an AMD EPYC chip with twice the cores for about the same price you'd pay only for the CPU part of this chip/half the intel cores.
- baybal2 8y ago>Also you can buy an AMD EPYC chip with twice the cores for about the same price you'd pay only for the CPU part of this chip/half the intel cores. Indeed. What benefits the most from being turned into FPGA circuit are stateless or minimally stateful circuits like media decoders/encoders. Complex stuff like fancy routers, classifiers, internet protocol inspection/handling will not gain a hundredfold speedup unlike the stuff above. This is why cheap x86 based routers are still a thing. At the moment, I am involved with one cloud provider in China that bids big on cheap FPGAs and RDMA. AWS and Azures can be defeated in detail. The plan is following: provide hardware accelerated "building blocks" of any modern dotcom business. Need memcached? We have it running on RDMA, from a bare metal ASIC, 10 times faster than any x86. Need transcoding? We have it available on RDMA, from a bare metal ASIC, 10 times cheaper than any AWS instance on buck/megabyte. Need API proxy for TLS/Gzip with gigabytes per second throughput? We have it running on RDMA, from a box with 4 PCIe accelerators, and AWS has nothing to offer for this use case other than "buy a hundred of top tier high performance instances and put them behind load balancers"
- sddfd 8y agoThis is great! I think that some time in the future, FPGA will be a vital part for data processing. In theory, an application with a computation-heavy task could program the FPGA to provide part of that task in hardware (think the hot innermost loop body). What I am worried about is the infrastructure that is needed to make this happen: Is there even support for this in our compilers? What would support look like?
- chrisseaton 8y ago> Is there even support for this in our compilers? What would support look like? FPGA offload has been a very active area of compiler research for more than a decade. I like this paper for example https://dri.es/files/fpl05-paper.pdf https://dri.es/files/fpl05-paper.pdf
- baybal2 8y agoThere is software that can poorly map OpenCL calls onto HDL code. It is still light years behind a human designer.
- qubex 8y agoBack in the mid-to-late nineties, Federico Faggin, designer of Intel's seminal 4004 (and ancestor of the whole x86 lineage) co-founded a company called Starbridge Systems that aimed to construct and sell what they termed hypercomputers whose architecture was rapidly-reconfiguring FPGAs that an enabled a compile-to-hardware model. Here's one of the few references to that project that I can now find online, a WIRED era piece with all the gushing nerd optimism of the pre-dot-com-bust: https://www.wired.com/1999/02/the-super-duper-hypercomputer/ https://www.wired.com/1999/02/the-super-duper-hypercomputer/ I suppose this is where Intel is headed now with these first few tentative steps.
- zantana 8y agoIsn't this what Transmeta was also trying to do? https://en.wikipedia.org/wiki/Transmeta https://en.wikipedia.org/wiki/Transmeta
- pjc50 8y ago
- chx 8y agoOn a whole different level, if you are merely interested in FPGAs in your computer then the PicoEVB neatly goes in the same M.2 slot as wifi cards do and communicates over PCIe, even if just PCIe Gen 2 x1. As far as I am aware this is, by far, the cheapest way to get an FPGA on the PCIe bus.
- convery 8y agoCool, will check it out. Thanks for sharing.
- kristianp 8y agoDon't new laptops only have one of those, for their hard drives?
- agumonkey 8y agoIt's confusing me. wifi cards don't need m2 slot, I thought it was a standard made for SSDs. Usually wifi cards use basic mini pcie sockets, even on old (2006>) 12" laptops you can find 2, albeit sometimes only one socket is installed (the other is empty space with pins there, some people even soldered one manually)
- loa-in-backup 8y agoDirectly from Wikipedia: Buses exposed through the M.2 connector are PCI Express 3.0, Serial ATA (SATA) 3.0 and USB 3.0, which is backward compatible with USB 2.0. As a result, M.2 modules can integrate multiple functions, including the following device classes: Wi-Fi, Bluetooth, satellite navigation, near field communication (NFC), digital radio, Wireless Gigabit Alliance (WiGig), wireless WAN (WWAN), and solid-state drives (SSDs).
- chx 8y agoM.2 slots come with different keys for different purposes. key B is used for WWAN and mostly SATA SSDs (although some slower NVMe drives ship with key B+M , the plus sign means it works in both slots). key M is used for x4 NVMe SSDs. And key E is used for wifi. And this card here.
- Keyframe 8y agoDepending on the price, this will be interesting for I/do-something/O workloads like video encoding/decoding. Depending on the price, looking forward to it. Of course, depending on the price. :)
- thesz 8y agoYou won't have enough resources for video encoding, most probably. Arria 10 FPGA has 67M bits of memory total (8.5M bytes), including one simulated with registers. As far as I remember, just storing 1920x1080 (HD) frame in 4:2:0 mode would require 4M bytes, half of memory. 4K would require 4 times as much resources. You may do some on-line processing like running neural net on the video content, but that's about it. Don't expect anything super exciting from that chip. Yet, it will bring joy to high frequency traders. The systems there do most of the work in FPGA, including UDP/TCP/IP packets processing and offload some work to CPU (broadcasts about network topology are handled on CPU, for example). They also would like to receive CPU computation results as fast as they can and this chip is exactly that.
- pjc50 8y agoYou have more than enough resources for video encoding, because all modern codecs have a macroblock structure. You don't need to keep the whole current frame in at once, you can slide a window around it. (Conversely, you do need to keep the matching area of the previous frame and maybe even the next frame in order to do proper inter-prediction). That said I would assume GPUs are more suited to this task. By FPGA standards this thing is enormous.
- thesz 8y agoYou are also limited by number of access paths into the memory which holds, say, macroblock. I forgot about this issue, sorry. For block RAM in previous generation FPGAs from Altera there were one read and one write paths. To have two read paths you would need to copy block RAM as many times as you need read paths. This means that if you search for block content inside a macroblock with N parallel accesses you would need N copies of macroblock stored. Tabula's time shifting tech allowed for up to, I believe, twelve paths into the block RAM, six for read and six for write (they were time-scheduled to 1-read-1-write block RAM operating at six times the frequency). I thought this thing would be a road for superscalar FPGA CPUs, but Tabula was closed. You can imagine not using RAM at all, but then you will spend other resources in FPGA. These are problems with video compression I see here. I think they are substantial but not unsurmountable and require a balance to solve. It is just me that I saw the balance is not in favour of FPGA.
- pjc50 8y agoNote that this is a ~$2500 processor with a ~$5000 FPGA stuck to it.
- exabrial 8y agoThis is cool! I have so many questions, like how does it work with context switching? How do they protect access to the cache?
- ManuelKiessling 8y agoThey don't, it's an Intel CPU.
- jdubs 8y agoLooks like a future AWS instance type.
- Someone 8y agoI thought FPGAs were limited to either cases where you need some custom hardware _now_ or where demand is low because, if demand is high enough and you can wait, custom ASICs are cheaper, lower power, and faster. What has changed here? Are FPGAs faster now or are many more people experimenting, creating sufficient demand for custom hardware at short notice?
- slededit 8y agoCPU performance increases are a lot slower now so it now makes sense to spend time on custom RTL. In the past you would just wait 8 months and buy the new twice as fast CPU. FPGAs are a waste of Silicon compared to ASICs, but for fixed applications they are less wasteful than CPUs.
- kbradero 8y agodoes it mean that you can load your designs on that fpga ? where can we find what features are exposed to sw ?